Method of making flash memory cell

Claim 1

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell and being patterned for preventing electron leakage of a gate of said memory cell during erasure; and forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate, said step of forming at least one peripheral transistor further including forming said gate of said peripheral transistor with said one of said at least two patterned polysilicon layers for preventing electron leakage of said gate of said memory cell during erasure.

Claim 2

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell and being patterned for preventing electron leakage of a gate of said memory cell during erasure; and forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate, said step of forming at least one peripheral transistor further including forming said gate of said peripheral transistor with said one of said at least two patterned polysilicon layers for preventing electron leakage of said gate of said memory cell during erasure.

Claim 18

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate formed from said one of said at least two patterned polysilicon layers; lightly doping an area of said substrate aligned with a sidewall of a memory cell gate formed with one of said remaining polysilicon layers; heavily doping an area in a portion of said substrate adjacent said lightly doped area; and forming said one of said at least two polysilicon layers in a step configuration, a portion of said one of said at least two polysilicon layers in said step configuration being formed over said lightly doped area, and said heavily doped area being formed in substantial alignment with a sidewall of said one of said at least two polysilicon layers which is formed in said step configuration.

Claim 19

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate formed from said one of said at least two patterned polysilicon layers; lightly doping an area of said substrate aligned with a sidewall of a memory cell gate formed with one of said remaining polysilicon layers; heavily doping an area in a portion of said substrate adjacent said lightly doped area; and forming said one of said at least two polysilicon layers in a step configuration, a portion of said one of said at least two polysilicon layers in said step configuration being formed over said lightly doped area, and said heavily doped area being formed in substantial alignment with a sidewall of said one of said at least two polysilicon layers which is formed in said step configuration.

Claim 20

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate formed from said one of said at least two patterned polysilicon layers; patterning a first of said at least two patterned polysilicon layers of the memory cell over the substrate; patterning a second of said at least two patterned polysilicon layers over a portion of said first patterned polysilicon layer; patterning said one of said at least two polysilicon layers adjacent said first and second polysilicon layers; and spacing a sidewall of said second patterned polysilicon layer from a sidewall of said first patterned polysilicon layer to form a step configuration.

Claim 21

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate formed from said one of said at least two patterned polysilicon layers; patterning a first of said at least two patterned polysilicon layers of the memory cell over the substrate; patterning a second of said at least two patterned polysilicon layers over a portion of said first patterned polysilicon layer; patterning said one of said at least two polysilicon layers adjacent said first and second polysilicon layers; and spacing a sidewall of said second patterned polysilicon layer from a sidewall of said first patterned polysilicon layer to form a step configuration.

Claim 22

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate formed from said one of said at least two patterned polysilicon layers, wherein said step of forming at least one peripheral transistor further including a step of: forming said gate of said peripheral transistor from a polysilicon layer formed adjacent a sidewall of at least one of a control gate and a floating gate of said memory cell.

Claim 23

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate formed from said one of said at least two patterned polysilicon layers, wherein said step of forming at least one peripheral transistor further including a step of: forming said gate of said peripheral transistor from a polysilicon layer formed adjacent a sidewall of at least one of a control gate and a floating gate of said memory cell.

Claim 24

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; and forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate formed from said one of said at least two patterned polysilicon layers, said step of forming at least one peripheral transistor further including a step of: forming said gate of said peripheral transistor with a polysilicon layer used for source side hot electron injection of said memory cell.

Claim 25

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; and forming at least one peripheral transistor on said substrate, said at least one peripheral transistor having a gate formed from said one of said at least two patterned polysilicon layers, said step of forming at least one peripheral transistor further including a step of: forming said gate of said peripheral transistor with a polysilicon layer used for source side hot electron injection of said memory cell.

Claim 26

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; lightly doping an area of said substrate aligned with a sidewall of a memory cell gate formed with one of said remaining polysilicon layers; heavily doping an area in a portion of said substrate adjacent said lightly doped area; and forming said one of said at least two polysilicon layers in a step configuration, a portion of said one of said at least two polysilicon layers in said step configuration being formed over said lightly doped area, and said heavily doped area being formed in substantial alignment with a sidewall of said one of said at least two polysilicon layers which is formed in said step configuration.

Claim 27

A method of manufacturing a multilayer polysilicon device including peripheral transistors, said method comprising the steps of: forming a memory cell having at least two patterned polysilicon layers on a substrate, with one of said at least two patterned polysilicon layers being patterned subsequent to formation of remaining polysilicon layers used to form said memory cell; lightly doping an area of said substrate aligned with a sidewall of a memory cell gate formed with one of said remaining polysilicon layers; heavily doping an area in a portion of said substrate adjacent said lightly doped area; and forming said one of said at least two polysilicon layers in a step configuration, a portion of said one of said at least two polysilicon layers in said step configuration being formed over said lightly doped area, and said heavily doped area being formed in substantial alignment with a sidewall of said one of said at least two polysilicon layers which is formed in said step configuration.