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US5120673A Expired / Lapsed US ⏱️ 0.0 years remaining

Process of fabricating field effect transistor with ldd structure

Assignee: NEC Corp
•
Filing: 1991-01-25
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Granted: 1992-06-09
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Expires: 2011-01-25
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Abstract

Abstract For formation of the LDD structure with stable impurity profiles, a first ion-implantation using a gate electrode as a mask is carried out through a gate oxide film for doping the semiconductor substrate with impurity atoms, covering the entire surface of the structure with a doped polysilicon film overlain by a protective oxide film, covering the protective oxide film with an intentionally undoped polysilicon film, anisotropically etching the intentionally undoped polysilicon film for forming a side wall on both sides of the side wall, removing exposed portions of the protective oxide film, carrying out a second ion-implantation using the gate electrode and the side wall as a mask for doping the semiconductor substrate with impurity atoms again, thereby forming heavily doped impurity regions partially overlapped with lightly doped impurity regions.

Inventors

  • 👤 Hiroshi Itoh

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 10:52
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/021; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; Y; Y10; Y10S; Y10S148/00; Y10S148/082

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 230 words
A process of fabricating a field effect transistor comprising the steps of: a) preparing a semiconductor substrate of a first conductivity type having a major surface; b) forming a gate oxide film on said major surface; c) forming a gate electrode on a predetermined portion of said gate oxide film; d) carrying out a first ion-implantation through said gate oxide film for doping said semiconductor substrate with impurity atoms of a second conductivity type opposite to said first conductivity type, thereby forming lightly doped impurity regions, said gate electrode serving as a mask during said first ion-implantation; e) covering the entire surface of the structure with doped polysilicon film overlain by a protective oxide film; f) covering said protective oxide film with an intentionally undoped polysilicon film; g) anisotropically etching said intentionally undoped polysilicon film for forming a side wall on a portion of said protective oxide film covering a side surface of said gate electrode, said protective oxide film being exposed on both sides of said side wall; h) removing exposed portions of said protective oxide film substantially without etching said doped polysilicon; i) carrying out a second ion-implantation through said doped polysilicon using said gate electrode and said side wall as a mask for doping said semiconductor substrate with impurity atoms of said second conductivity type, thereby forming heavily doped impurity regions; and j) removing said side wall.
Claim 2
Dependent Claim 230 words
A process of fabricating a field effect transistor comprising the steps of: a) preparing a semiconductor substrate of a first conductivity type having a major surface; b) forming a gate oxide film on said major surface; c) forming a gate electrode on a predetermined portion of said gate oxide film; d) carrying out a first ion-implantation through said gate oxide film for doping said semiconductor substrate with impurity atoms of a second conductivity type opposite to said first conductivity type, thereby forming lightly doped impurity regions, said gate electrode serving as a mask during said first ion-implantation; e) covering the entire surface of the structure with doped polysilicon film overlain by a protective oxide film; f) covering said protective oxide film with an intentionally undoped polysilicon film; g) anisotropically etching said intentionally undoped polysilicon film for forming a side wall on a portion of said protective oxide film covering a side surface of said gate electrode, said protective oxide film being exposed on both sides of said side wall; h) removing exposed portions of said protective oxide film substantially without etching said doped polysilicon; i) carrying out a second ion-implantation through said doped polysilicon using said gate electrode and said side wall as a mask for doping said semiconductor substrate with impurity atoms of said second conductivity type, thereby forming heavily doped impurity regions; and j) removing said side wall.
Claim 3
Dependent Claim 27 words
A process as set forth in claim 1, in which said heavily doped impurity regions are formed in surface portions of said lightly doped impurity regions, respectively.
Claim 4
Dependent Claim 27 words
A process as set forth in claim 2, in which said gate electrode is formed of polysilicon and doped with said impurity atoms in said first ion-implantation.
Claim 5
Dependent Claim 24 words
A process as set forth in claim 3, in which said intentionally undoped polysilicon film is anisotropically etched by using a plasma etching technique.
Claim 6
Dependent Claim 36 words
A process as set forth in claim 4, in which said exposed portions of said protective oxide film and said exposed portions of said doped polysilicon film are successively etched by using said plasma etching technique.
Claim 7
Dependent Claim 24 words
A process as set forth in claim 4, in which phosphorus atoms and arsenic atoms are used in said first and second ion-implantations, respectively.
Claim 8
Dependent Claim 23 words
A process as set forth in claim 1, in which said lightly doped impurity regions are shallower than said heavily doped impurity regions.
Claim 9
Dependent Claim 23 words
A process as set forth in claim 1, in which exposed portions of said doped polysilicon film are removed after said step i).
Claim 10
Dependent Claim 27 words
A process as set forth in claim 8, in which said heavily doped impurity regions are respectively formed in surface portions of said lightly doped impurity regions.
Claim 11
Dependent Claim 33 words
A process as set forth in claim 9, in which said gate electrode is constituted by a combination of a polysilicon film, a film of a refractory metal silicide and an oxide film.
Claim 12
Dependent Claim 24 words
A process as set forth in claim 10, in which said intentionally undoped polysilicon film is anisotropically etched by using a plasma etching technique.
Claim 13
Dependent Claim 24 words
A process as set forth in claim 11, in which phosphorus atoms and arsenic atoms are used in said first and second ion-implantations, respectively.

References Cited (Backward Citations)

US4735680A Cited
US4808544A Cited
US4837180A Cited
US4963504A Cited
US4906589A Cited
US4984042A Cited
US4951100A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-06-09 1995-12-09 1996-06-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-06-09 1999-12-09 2000-06-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-06-09 2003-12-09 2004-06-09 $7700.00 Window Closed / Lapsed

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