US5584009A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method of retiring store data from a write buffer
Assignee: VIA Cyrix Inc
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Filing: 1993-10-18
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Granted: 1996-12-10
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Expires: 2013-10-18
Abstract
Abstract A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.
Inventors
- 👤 Raul A. Garibay, Jr.
- 👤 Marc A. Quattromani
- 👤 Mark Bluhm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:51
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F9/30181; G06F9/38; G06F9/3802; G06F9/3816; G06F9/3824; G06F9/3834; G06F9/3836; G06F9/3842; G06F9/3854; G06F9/3858; G06F9/3861; G06F9/3865; G06F12/04
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
208 words
A microprocessor, comprising: a central processing unit core, for processing data according to operations defined by instructions to be executed in a program order, wherein at least one of said instructions is of a conditional branch type; a write buffer having a plurality of buffer entries, coupled to said central processing unit core, for receiving data therefrom corresponding to results of said instructions, wherein each of said buffer entries includes at least one speculation control bit indicating, when set, that data to be written to each of said buffer entries is from the execution of an instruction in a predicted branch in program order after an instruction of the conditional branch type; a cache, having a plurality of locations, said cache coupled to said write buffer for receiving data therefrom, and coupled to said central processing unit core for presenting data thereto; a memory bus, coupled to said central processing unit core, said write buffer, and said cache, for receiving data from and presenting data to said cache; and control logic for controlling the presenting of data by said write buffer to said cache so that the contents of each of said buffer entries are presented to said cache only if the speculation control bit is not set.
Claim 2
Dependent Claim
208 words
A microprocessor, comprising: a central processing unit core, for processing data according to operations defined by instructions to be executed in a program order, wherein at least one of said instructions is of a conditional branch type; a write buffer having a plurality of buffer entries, coupled to said central processing unit core, for receiving data therefrom corresponding to results of said instructions, wherein each of said buffer entries includes at least one speculation control bit indicating, when set, that data to be written to each of said buffer entries is from the execution of an instruction in a predicted branch in program order after an instruction of the conditional branch type; a cache, having a plurality of locations, said cache coupled to said write buffer for receiving data therefrom, and coupled to said central processing unit core for presenting data thereto; a memory bus, coupled to said central processing unit core, said write buffer, and said cache, for receiving data from and presenting data to said cache; and control logic for controlling the presenting of data by said write buffer to said cache so that the contents of each of said buffer entries are presented to said cache only if the speculation control bit is not set.
Claim 3
Dependent Claim
28 words
The microprocessor of claim 1, wherein said control logic is also for clearing the speculation control bits of the buffer entries responsive to the predicted branch being successful.
Claim 4
Dependent Claim
30 words
The microprocessor of claim 2, wherein, in the event of an unsuccessful predicted branch, said control logic is also for invalidating each buffer entry having its speculation control bit set.
Claim 5
Dependent Claim
59 words
The microprocessor of claim 1, wherein each of said buffer entries includes a plurality of speculation control bits, each speculation control bit corresponding to one predicted branch; and wherein said control logic is also for setting those speculation control bits for a buffer entry corresponding to predicted branches upon which the write of data to the buffer entry depend.
Claim 6
Dependent Claim
30 words
The microprocessor of claim 4, wherein said control logic is also for clearing the speculation control bits of the buffer entries, responsive to the successful completion of a predicted branch.
Claim 7
Dependent Claim
36 words
The microprocessor of claim 5, wherein, responsive to an unsuccessful predicted branch, said control logic is also for invalidating each of the buffer entries having the speculation control bit corresponding to the unsuccessful predicted branch set.
Claim 8
Dependent Claim
106 words
The microprocessor of claim 1, wherein said control logic further comprises: a retire pointer for indicating the next buffer entry that is to have its contents presented to said cache; and an allocation pointer for indicating the next buffer entry that is to be allocated to receive the results of an instruction; wherein said buffer entries each further include a no-op control bit for causing, when set, the retire pointer to skip the buffer entry; and wherein said control logic is also for setting the no-op control bit in each of the buffer entries having the speculation control bit corresponding to an unsuccessful predicted branch set.
Claim 9
Dependent Claim
130 words
The microprocessor of claim 1, wherein each of said buffer entries includes an address valid control bit indicating, when set, that the buffer entry has had a memory address assigned thereto and is reserved for subsequent writing of data thereto by the central processing unit core, and also includes a data valid control bit indicating, when set, that the buffer entry has had valid data written thereto by the central processing unit core; wherein said central processing unit core is also for detecting the occurrence of an exception condition; and wherein said control logic is also for clearing the address valid control bit in each write buffer entry that has its address valid control bit set and its data valid control bit clear, responsive to detection of an exception condition.
Claim 10
Independent Claim
230 words
A method of buffering results of data processing operations executed by a central processing unit core of a pipelined type in a microprocessor according to a series of instructions including at least one instruction of a conditional branch type, such buffering being effected in a write buffer having a plurality of write buffer entries and effected prior to storage in a cache of the microprocessor, comprising the steps of: responsive to detecting a first conditional instruction of the conditional branch type, predicting a first sequence of instructions to be executed prior to determining a state of a condition upon which the first conditional instruction depends; for a first write instruction in a first predicted sequence corresponding to a memory write, determining a first physical address to which results are to be written; storing the first physical address in a first write buffer entry; executing the first write instruction in the first predicted sequence; storing results of the first write instruction in the first write buffer entry; determining the state of the condition upon which the first conditional instruction depends; and responsive to said step of determining the state of the condition upon which the first conditional instruction depends, indicating that said step of predicting a first sequence of instructions was correct, retrieving the results of the first write instruction in the first write buffer entry for storage in said cache.
Claim 11
Independent Claim
230 words
A method of buffering results of data processing operations executed by a central processing unit core of a pipelined type in a microprocessor according to a series of instructions including at least one instruction of a conditional branch type, such buffering being effected in a write buffer having a plurality of write buffer entries and effected prior to storage in a cache of the microprocessor, comprising the steps of: responsive to detecting a first conditional instruction of the conditional branch type, predicting a first sequence of instructions to be executed prior to determining a state of a condition upon which the first conditional instruction depends; for a first write instruction in a first predicted sequence corresponding to a memory write, determining a first physical address to which results are to be written; storing the first physical address in a first write buffer entry; executing the first write instruction in the first predicted sequence; storing results of the first write instruction in the first write buffer entry; determining the state of the condition upon which the first conditional instruction depends; and responsive to said step of determining the state of the condition upon which the first conditional instruction depends, indicating that said step of predicting a first sequence of instructions was correct, retrieving the results of the first write instruction in the first write buffer entry for storage in said cache.
Claim 12
Dependent Claim
25 words
The method of claim 9, further comprising: responsive to said determining step indicating that said predicting step was incorrect, invalidating the first write buffer entry.
Claim 13
Dependent Claim
34 words
The method of claim 10, further comprising: after said step of storing the first physical address in a first write buffer entry, setting an address valid control bit in the first write buffer entry.
Claim 14
Dependent Claim
22 words
The method of claim 11, wherein said invalidating step comprises: clearing the address valid control bit in the first write buffer entry.
Claim 15
Dependent Claim
40 words
The method of claim 12, wherein said invalidating step further comprises: setting a no-op control bit in the first write buffer entry, so that said first write buffer entry will be skipped in retrieving of data from the write buffer.
Claim 16
Dependent Claim
137 words
The method of claim 9, further comprising: prior to said step of determining the state of the condition upon which the first conditional instruction depends, for a second write instruction in the first predicted sequence corresponding to a memory write, determining a second physical address to which results are to be written; storing the second physical address in a second write buffer entry; executing the second write instruction in the first predicted sequence; storing results of the second write instruction in the second write buffer entry; and responsive to said step of determining the state of the condition upon which the first conditional instruction depends indicating that said step of predicting a first sequence of instructions was correct, retrieving the results of the second write instruction in the second write buffer entry for storage in said cache.
Claim 17
Dependent Claim
95 words
The method of claim 14, further comprising: after each of said steps of storing the first and second physical addresses, setting a speculation control bit in each of said first and second write buffer entries; and responsive to said step of determining the state of the condition upon which the first conditional instruction depends, indicating that said step of predicting a first sequence of instructions was incorrect, testing each write buffer entry to determine if its speculation control bit is set and, if so, invalidating the write buffer entry having its speculation control bit set.
Claim 18
Dependent Claim
180 words
The method of claim 9, further comprising: responsive to detecting a second conditional instruction of the conditional branch type in the first predicted sequence and prior to said step of determining the condition upon which the first conditional instruction depends, predicting a second sequence of instructions to be executed prior to determining the state of a condition upon which the second conditional instruction depends; for a write instruction in the second predicted sequence corresponding to a memory write, determining a second physical address to which results are to be written; storing the second physical address in a second write buffer entry; executing the write instruction of the second predicted sequence; storing results of the write instruction of the second predicted sequence in the second write buffer entry; determining a condition upon which the second conditional instruction depends; and responsive to said step of determining the condition upon which the second conditional instruction depends, indicating that said step of predicting a second sequence of instructions was correct, retrieving the results in the second write buffer entry for storage in said cache.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |