High-voltage CMOS transistors on a standard CMOS wafer

Claim 3

The method of claim 1, wherein the step of implanting an n-type impurity to form a heavily doped n+ buried layer further comprises the step of implanting arsenic at an energy of about 160 KeV to achieve a concentration of about 10 13 to 10 14 atoms/cm 2 in the buried layer.

Claim 4

The method of claim 1, wherein the step of implanting an n-type impurity to form a heavily doped n+ buried layer further comprises the step of implanting phosphorus at an energy of about 140 to 200 KeV to achieve a concentration of about 10 16 to 10 17 atoms/cm 2 in the buried layer.

Claim 5

The method of claim 1, wherein the first epitaxial layer has a thickness of about 22 μm and the second epitaxial layer has a thickness of about 1.8 μm.

Claim 6

The method of claim 2, further comprising the steps of: forming a thin layer of oxide over the first epitaxial layer; selectively masking the thin layer of oxide so a selected portion of the oxide defining the heavily doped n+ buried layer is exposed; implanting the arsenic through the selected portion of the oxide to form the heavily doped n+ buried layer in the first epitaxial layer; removing the mask and the layer of oxide; forming the second epitaxial layer and a first pad oxide on the second epitaxial layer; forming a layer of silicon nitride over the first pad oxide; selectively removing the layer of silicon nitride in a selected site defining the n-well; implanting phosphorus to form the n-well, the phosphorus having an energy of about 140 KeV and provided at a sufficient dosage to achieve a concentration of about 4.5×10 12 atoms/cm 2 ; forming oxide using LOCOS; removing the layer of silicon nitride; etching back the oxide and driving in the n-well by heating to 1150 degrees celsius to drive in the phosphorus to increase the depth of the n-well to substantially the depth of the second epitaxial layer; forming a second pad oxide, a composite nitride, and a mask to expose a selected site defining a p-field extension region within the n-well; and implanting BF 2 to form the p-field extension region, the BF 2 provided with an energy of about 140 KeV to achieve a concentration of about 5.5×10 13 atoms/cm 2 .

Claim 9

The method of claim 6, wherein the arsenic is implanted an energy of about 160 KeV to achieve a concentration of about 10 13 to 10 14 atoms/cm 2 in the buried layer.

Claim 10

The method of claim 6, wherein the phosphorus is implanted at an energy of about 140 to 200 KeV to achieve a concentration of about 10 16 to 10 17 atoms/cm 2 in the buried layer.

Claim 11

The method of claim 6, wherein the BF 2 is implanted at an energy of about 140 KeV to achieve a concentration of about 5.5×10 13 atoms/cm 2 .

Claim 12

A CMOS device having an increased operating voltage range, comprising: a p-type substrate having a surface; a lightly doped p-type first epitaxial layer on the surface; a lightly doped p-type second epitaxial layer on the first epitaxial layer; an n-well within the second epitaxial layer; a source region within the n-well; a drain region within the n-well; conduction means, within the first epitaxial layer, for increasing capacity for current to pass between the source region and the drain region during operation of the device; and extension means, within the second epitaxial layer, for reducing constraints upon an electric field surrounding the drain region generated during operation of the device to increase breakdown and punch-through voltage thresholds of the device.

Claim 13

A CMOS device having an increased operating voltage range, comprising: a p-type substrate having a surface; a lightly doped p-type first epitaxial layer on the surface; a lightly doped p-type second epitaxial layer on the first epitaxial layer; an n-well within the second epitaxial layer; a source region within the n-well; a drain region within the n-well; conduction means, within the first epitaxial layer, for increasing capacity for current to pass between the source region and the drain region during operation of the device; and extension means, within the second epitaxial layer, for reducing constraints upon an electric field surrounding the drain region generated during operation of the device to increase breakdown and punch-through voltage thresholds of the device.

Claim 14

The CMOS device of claim 10, wherein the conduction means comprises a heavily doped n+ buried layer within the first epitaxial layer, the buried layer formed from implanted arsenic at an energy of about 160 KeV to achieve a concentration of about 10 13 to 10 14 atoms/cm 2 in the buried layer.

Claim 15

The CMOS device of claim 10, wherein the conduction means comprises a heavily doped n+ buried layer within the first epitaxial layer, the buried layer formed from implanted phosphorus at an energy of about 140 to 200 KeV to achieve a concentration of about 10 16 to 10 17 atoms/cm 2 in the buried layer.

Claim 16

The CMOS device of claim 10, wherein the extension means comprises a p-field extension region formed from implanted BF 2 at an energy of about 140 KeV to achieve a concentration of about 5.5×10 13 atoms/cm 2 .

Claim 17

A CMOS device having an increased operating voltage range, comprising: a p-type substrate; a first epitaxial layer on the p-type substrate, the first epitaxial layer comprising lightly doped p-type material; a buried layer within the first epitaxial layer, the buried layer comprising an n-type impurity at a sufficient concentration to provide a heavily doped n+ region; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer comprising lightly doped p-type material and further including: an n-well having a drain region; and a p-field extension region surrounding the drain region.

Claim 18

A CMOS device having an increased operating voltage range, comprising: a p-type substrate; a first epitaxial layer on the p-type substrate, the first epitaxial layer comprising lightly doped p-type material; a buried layer within the first epitaxial layer, the buried layer comprising an n-type impurity at a sufficient concentration to provide a heavily doped n+ region; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer comprising lightly doped p-type material and further including: an n-well having a drain region; and a p-field extension region surrounding the drain region.

Claim 19

The CMOS device of claim 14, wherein the buried layer comprises arsenic implanted at an energy of about 160 KeV to achieve a concentration of about 10 13 to 10 14 atoms/cm 2 .

Claim 20

The CMOS device of claim 14, wherein the buried layer comprises phosphorus implanted at an energy of about 140 to 200 KeV to achieve a concentration of about 10 16 to 10 17 atoms/cm 2 .

Claim 21

The CMOS device of claim 14, wherein the p-field extension region comprises BF 2 implanted at an energy of about 140 KeV to achieve a concentration of about 5.5×10 13 atoms/cm 2 .