Personalized area leadframe coining or half etching for reduced mechanical stress at device edge

Abstract

Abstract A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides increasing path length to prevent corrosive ingress over the chip face.

Inventors

• 👤 Harold W. Conru
• 👤 Francis E. Froebel
• 👤 Albert J. Gregoritsch, Jr.
• 👤 Sheldon C. Rieley
• 👤 Stephen G. Starr
• 👤 Ronald R. Uttecht
• 👤 Eric J. White
• 👤 Jens G. Pohl

Bibliographic Details