Patent US5573960A successfully refreshed from Google Patents.
US5573960A
Expired / Lapsed
US
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Method of manufacturing semiconductor layers by bonding without defects created by bonding
Assignee: Mitsubishi Electric Corp
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Filing: 1995-07-10
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Granted: 1996-11-12
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Expires: 2015-07-10
Abstract
Abstract A method of manufacturing a semiconductor layer includes preparing a first semiconductor substrate; forming an etching stop layer on the surface of the first substrate; forming an active layer on the etching stop layer; forming a crystal defect reducing layer on the active layer; preparing a second semiconductor substrate having a heat conductivity higher than the heat conductivity of the first substrate; bonding the crystal defect reducing layer to the second substrate; selectively etching the first substrate to expose the etching stop layer; selectively etching the etching stop layer to expose the active layer, whereby the active layer is disposed on the second substrate with the crystal defect reducing layer therebetween. The heat dissipation property is significantly improved by the second substrate having a high heat conductivity and by reducing the thicknesses of the active layer and the crystal defect reducing layer. In addition, good crystallinity of the active layer and sufficient mechanical strength of the substrate are obtained.
Inventors
- 👤 Shigekazu Izumi
- 👤 Norio Hayafuji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:37
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/70; H10P72/74; H10W; H10W40/00; H10W40/20; H10W40/25; H10W40/255; H10W72/00; H10W72/30; H10P72/743; H10P72/7432; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/051; Y10S148/072; Y10S148/15; Y10S438/00; Y10S438/933
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
183 words
A method of manufacturing a semiconductor layer structure comprising: preparing a first substrate having a surface and comprising a crystalline semiconductor having a heat conductivity; forming an etch stopping layer on the surface of the first substrate; forming an active layer as a constituent of a semiconductor device on the etch stopping layer; forming a crystalline semiconductor defect reducing layer on the active layer; preparing a second substrate having a surface and comprising a material having a heat conductivity higher than the heat conductivity of the first substrate; bonding the defect reducing layer to the surface of the second substrate at an elevated temperature, the defect reducing layer preventing crystalline defects caused by the bonding from extending to the active layer; selectively etching the first substrate to expose the etch stopping layer; and selectively etching the etch stopping layer to expose the active layer, whereby the active layer is supported by the second substrate with the defect reducing layer therebetween so that crystalline defects caused by the bonding are confined to the defect reducing layer and do not extend to the active layer.
Claim 2
Independent Claim
183 words
A method of manufacturing a semiconductor layer structure comprising: preparing a first substrate having a surface and comprising a crystalline semiconductor having a heat conductivity; forming an etch stopping layer on the surface of the first substrate; forming an active layer as a constituent of a semiconductor device on the etch stopping layer; forming a crystalline semiconductor defect reducing layer on the active layer; preparing a second substrate having a surface and comprising a material having a heat conductivity higher than the heat conductivity of the first substrate; bonding the defect reducing layer to the surface of the second substrate at an elevated temperature, the defect reducing layer preventing crystalline defects caused by the bonding from extending to the active layer; selectively etching the first substrate to expose the etch stopping layer; and selectively etching the etch stopping layer to expose the active layer, whereby the active layer is supported by the second substrate with the defect reducing layer therebetween so that crystalline defects caused by the bonding are confined to the defect reducing layer and do not extend to the active layer.
Claim 3
Dependent Claim
11 words
The method of claim 1 wherein the first substrate comprises GaAs.
Claim 4
Dependent Claim
11 words
The method of claim 2 wherein the second substrate comprises GaP.
Claim 5
Dependent Claim
11 words
The method of claim 2 wherein the second substrate comprises Si.
Claim 6
Dependent Claim
46 words
The method of claim 2 including: preparing an Si substrate and an SiO 2 film much thinner than the Si substrate and disposed on the surface of the Si substrate as the second substrate; and bonding the crystal defect reducing layer to the SiO 2 film.
Claim 7
Dependent Claim
11 words
The method of claim 1 wherein the first substrate comprises InP.
Claim 8
Dependent Claim
11 words
The method of claim 6 wherein the second substrate comprises Si.
Claim 9
Dependent Claim
46 words
The method of claim 6 including: preparing an Si substrate and an SiO 2 film much thinner than the Si substrate and disposed on the surface of the Si substrate as the second substrate; and bonding the crystal defect reducing layer to the SiO 2 film.
Claim 10
Dependent Claim
33 words
The method of claim 1 including producing, as the active layer, a plurality of semiconductor layers for forming emitter, base, and collector layers of a heterojunction bipolar transistor on the etch stopping layer.
Claim 11
Dependent Claim
12 words
The method of claim 3 wherein the defect reducing layer is GaAs.
Claim 12
Dependent Claim
12 words
The method of claim 4 wherein the defect reducing layer is GaAs.
Claim 13
Dependent Claim
12 words
The method of claim 5 wherein the defect reducing layer is GaAs.
Claim 14
Dependent Claim
12 words
The method of claim 7 wherein the defect reducing layer is InP.
Claim 15
Dependent Claim
12 words
The method of claim 8 wherein the defect reducing layer is InP.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-12 | 2000-05-13 | 2000-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-12 | 2004-05-13 | 2004-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-12 | 2008-05-13 | 2008-11-12 | $7700.00 | Window Closed / Lapsed |