US5324678A
Expired / Lapsed
US
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Method of forming a multi-layer type semiconductor device with semiconductor element layers stacked in opposite directions
Assignee: Mitsubishi Electric Corp
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Filing: 1992-11-30
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Granted: 1994-06-28
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Expires: 2012-11-30
Abstract
Abstract A multi-layer type semiconductor device is disclosed, in which a plurality of semiconductor layers are formed in vertically opposite directions. The multi-layer type semiconductor device is obtained by forming a first semiconductor layer, an insulating layer and a second semiconductor layer in the mentioned order on a main surface of a first substrate, forming a semiconductor device by using the second semiconductor layer as a base, with an exposed surface thereof directed upward, forming an insulating film on the semiconductor device, attaching a second substrate to the insulating film, thinning the first substrate to expose the first semiconductor layer, and forming a further semiconductor device by using the first semiconductor layer as a base, with an exposed surface of the first semiconductor layer directed upward. A single-chip type image forming system or sensing system may be provided by employing, as the semiconductor devices, a sensing device such as a photosensor, a pressure sensor or the like, a processing circuit for processing a signal received from the sensor, and a display device for displaying results of the processing. A large number of pads may be provided by arranging the pads on opposite surfaces of a chip.
Inventors
- 👤 Shigeru Kusunoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 00:00
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/80; H10F39/803; H10D; H10D88/00; H10F39/10; H10F39/12; H10F39/18; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1922; H10W; H10W10/00; H10W10/10; H10W10/181; H10P72/00; H10P72/70; H10P72/74; H10P72/7426; H10P72/7432; Y; Y10; Y10S; Y10S438/00; Y10S438/928
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
126 words
A method of manufacturing a multi-layer type semiconductor device comprising the steps of; forming a base member by successively stacking, on a main surface of a first substrate, a first semiconductor layer, an insulating layer and a second semiconductor layer, with said second semiconductor layer having a surface exposed outwardly, forming a semiconductor device by using said second semiconductor layer as a base with the exposed surface of said second semiconductor layer directed upward, forming an insulating film on said semiconductor device, attaching a second substrate to said insulating film, thinning said first substrate to expose said first semiconductor layer, and forming a further semiconductor device by using said first semiconductor layer as a base with an exposed surface of said first semiconductor layer directed upward.
Claim 2
Independent Claim
126 words
A method of manufacturing a multi-layer type semiconductor device comprising the steps of; forming a base member by successively stacking, on a main surface of a first substrate, a first semiconductor layer, an insulating layer and a second semiconductor layer, with said second semiconductor layer having a surface exposed outwardly, forming a semiconductor device by using said second semiconductor layer as a base with the exposed surface of said second semiconductor layer directed upward, forming an insulating film on said semiconductor device, attaching a second substrate to said insulating film, thinning said first substrate to expose said first semiconductor layer, and forming a further semiconductor device by using said first semiconductor layer as a base with an exposed surface of said first semiconductor layer directed upward.
Claim 3
Dependent Claim
89 words
A method of manufacturing a multi-layer type semiconductor device according to claim 1, wherein the step of forming the base member includes the steps of; bonding a first member including said first semiconductor layer formed on said first substrate, with a second member including said second semiconductor layer formed on a third substrate and said insulating layer formed on said second semiconductor layer, such that said insulating layer and said first semiconductor layer are opposed to each other, and thinning said third substrate the expose said second semiconductor layer.
Claim 4
Independent Claim
156 words
A method of manufacturing a multi-layer type semiconductor device comprising the steps of; forming perforations through a first substrate; filling said perforations with conductors, successively forming a first semiconductor layer on a main surface of a second substrate, an insulating layer on said first semiconductor layer, and a second semiconductor on said insulating layer, forming a first electric circuit on said insulating layer of said second substrate by using said second semiconductor layer as a base, and first pads electrically connected to said first electric circuit, bonding said first substrate and said second substrate so as to electrically interconnect said conductors of said first substrate and said first pads of said second substrate, thinning said second substrate to expose said first semiconductor layer, and forming a second electric circuit on said insulating layer of said second substrate by using said first semiconductor layer as a base, and second pads electrically connected to said second electric circuit.
Claim 5
Independent Claim
156 words
A method of manufacturing a multi-layer type semiconductor device comprising the steps of; forming perforations through a first substrate; filling said perforations with conductors, successively forming a first semiconductor layer on a main surface of a second substrate, an insulating layer on said first semiconductor layer, and a second semiconductor on said insulating layer, forming a first electric circuit on said insulating layer of said second substrate by using said second semiconductor layer as a base, and first pads electrically connected to said first electric circuit, bonding said first substrate and said second substrate so as to electrically interconnect said conductors of said first substrate and said first pads of said second substrate, thinning said second substrate to expose said first semiconductor layer, and forming a second electric circuit on said insulating layer of said second substrate by using said first semiconductor layer as a base, and second pads electrically connected to said second electric circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |