Method of manufacturing a bonded semiconductor substrate and a dielectric isolated bipolar transistor

Claim 1

A method of manufacturing a bonded semiconductor substrate, comprising the steps of: providing a first semiconductor substrate of silicon, having a top surface and a back surface, said top surface having thereon a SiGe mixed crystal layer, a silicon layer containing N-type impurities, a SiGe mixed crystal layer containing N-type impurities which are formed in order by epitaxial growth process; providing a second semiconductor substrate of a silicon substrate, having a top surface; providing a silicon oxide film on at least one of said top surface of said first semiconductor substrate and said top surface of said second semiconductor substrate; contacting said top surfaces of said first and second semiconductor substrates, at least one of which being provided with said silicon oxide film, and bonding said first and second semiconductor substrates to each other by heat treatment; etching said first semiconductor substrate from said back surface until said SiGe mixed crystal layer is exposed; and etching said SiGe mixed crystal layer until said silicon layer containing N-type impurities is exposed.

Claim 2

A method of manufacturing a bonded semiconductor substrate, comprising the steps of: providing a first semiconductor substrate of silicon, having a top surface and a back surface, said top surface having thereon a SiGe mixed crystal layer, a silicon layer containing N-type impurities, a SiGe mixed crystal layer containing N-type impurities which are formed in order by epitaxial growth process; providing a second semiconductor substrate of a silicon substrate, having a top surface; providing a silicon oxide film on at least one of said top surface of said first semiconductor substrate and said top surface of said second semiconductor substrate; contacting said top surfaces of said first and second semiconductor substrates, at least one of which being provided with said silicon oxide film, and bonding said first and second semiconductor substrates to each other by heat treatment; etching said first semiconductor substrate from said back surface until said SiGe mixed crystal layer is exposed; and etching said SiGe mixed crystal layer until said silicon layer containing N-type impurities is exposed.

Claim 3

A method of manufacturing a dielectric isolated bipolar transistor, comprising the steps of: providing a first semiconductor substrate of silicon; having a top surface and a back surface, said top surface having thereon a first SiGe mixed crystal layer containing N-type impurities, a first silicon layer containing N-type impurities, a second SiGe mixed crystal layer containing N-type impurities, and a second silicon layer containing N-type impurities, which are formed in order by epitaxial growth; providing a second semiconductor substrate of silicon, having a top surface; providing a silicon oxide film on at least one of said top surface of said first semiconductor substrate and said top surface of said second semiconductor substrate; contacting said top surfaces of said first and second semiconductor substrates, at least one of which being provided with said silicon oxide film, and bonding said first and second semiconductor substrates to each other by high-temperature heat treatment; etching said first semiconductor substrate from said back surface until said first SiGe mixed crystal layer is exposed; etching said first SiGe mixed crystal layer until said first silicon layer containing N-type impurities is exposed; providing first insulation films on portions of said first silicon layer containing N-type impurities, said portions serving as a base/emitter and a collector; etching said first silicon layer containing N-type impurities, using said first insulation films as masks and using said second SiGe mixed crystal layer containing N-type impurities of high concentration as an etching stopper; providing a second insulation film on a region other than an element isolation region; etching said second SiGe mixed crystal layer containing N-type impurities and said second silicon layer containing N-type impurities, using said second insulation film as a mask; and removing said first and second insulation films, providing a third insulation film over said first semiconductor substrate, and etching said third insulation film until said portions serving as the base/emitter and the collector are exposed.

Claim 4

A method of manufacturing a dielectric isolated bipolar transistor, comprising the steps of: providing a first semiconductor substrate of silicon; having a top surface and a back surface, said top surface having thereon a first SiGe mixed crystal layer containing N-type impurities, a first silicon layer containing N-type impurities, a second SiGe mixed crystal layer containing N-type impurities, and a second silicon layer containing N-type impurities, which are formed in order by epitaxial growth; providing a second semiconductor substrate of silicon, having a top surface; providing a silicon oxide film on at least one of said top surface of said first semiconductor substrate and said top surface of said second semiconductor substrate; contacting said top surfaces of said first and second semiconductor substrates, at least one of which being provided with said silicon oxide film, and bonding said first and second semiconductor substrates to each other by high-temperature heat treatment; etching said first semiconductor substrate from said back surface until said first SiGe mixed crystal layer is exposed; etching said first SiGe mixed crystal layer until said first silicon layer containing N-type impurities is exposed; providing first insulation films on portions of said first silicon layer containing N-type impurities, said portions serving as a base/emitter and a collector; etching said first silicon layer containing N-type impurities, using said first insulation films as masks and using said second SiGe mixed crystal layer containing N-type impurities of high concentration as an etching stopper; providing a second insulation film on a region other than an element isolation region; etching said second SiGe mixed crystal layer containing N-type impurities and said second silicon layer containing N-type impurities, using said second insulation film as a mask; and removing said first and second insulation films, providing a third insulation film over said first semiconductor substrate, and etching said third insulation film until said portions serving as the base/emitter and the collector are exposed.