US5563801A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process independent design for gate array devices
Assignee: Synopsys Inc
•
Filing: 1993-10-06
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Granted: 1996-10-08
•
Expires: 2013-10-06
Abstract
Abstract A unique gate array cell and ASIC library development methodology is taught which require no new simulations or new place and route to port a given device design to a same generation process technologies which are available from different vendors. This methodology make use of the minimum design rules from different vendors without reroute of the physical database. This methodology equalizes the functionality and timing characteristics of the macrocell library on a plurality of alternate sources.
Inventors
- 👤 Ven L. Lee
- 👤 Hemraj K. Hingarh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:11
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
268 words
A method of manufacturing an integrated circuit to perform a specified function, comprising the steps of: generating information corresponding to an electronic circuit designed to perform the specified function; determining characteristics of an integrated circuit fabricated using a first integrated circuit fabrication process, said characteristics including speed; establishing a general pattern for an integrated circuit, within which pattern will be placed specific circuit elements; developing a first layout for said integrated circuit, said first layout including location information for each transistor of said integrated circuit within said general pattern, wherein said developing step is performed using the information corresponding to the electronic circuit configured to perform the specified function and information corresponding to a first type integrated circuit fabrication process; determining characteristics of an integrated circuit fabricated using a second integrated circuit fabrication process, said characteristics including speed; determining differences in characteristics between an integrated circuit fabricated using said first fabrication process and an integrated circuit fabricated using said second fabrication process; developing a second layout for said integrated circuit, said second layout including location information for each transistor of said integrated circuit within said general pattern, wherein said developing step is performed using the information corresponding to the electronic circuit configured to perform the specified function, information corresponding to a second type integrated circuit fabrication process, and information corresponding to said first type integrated circuit fabrication process, and including the step of adjusting channel widths of transistors in said second layout based upon said differences in characteristics between an integrated circuit fabricated using said first fabrication process and an integrated circuit fabricated using said second fabrication process.
Claim 2
Independent Claim
268 words
A method of manufacturing an integrated circuit to perform a specified function, comprising the steps of: generating information corresponding to an electronic circuit designed to perform the specified function; determining characteristics of an integrated circuit fabricated using a first integrated circuit fabrication process, said characteristics including speed; establishing a general pattern for an integrated circuit, within which pattern will be placed specific circuit elements; developing a first layout for said integrated circuit, said first layout including location information for each transistor of said integrated circuit within said general pattern, wherein said developing step is performed using the information corresponding to the electronic circuit configured to perform the specified function and information corresponding to a first type integrated circuit fabrication process; determining characteristics of an integrated circuit fabricated using a second integrated circuit fabrication process, said characteristics including speed; determining differences in characteristics between an integrated circuit fabricated using said first fabrication process and an integrated circuit fabricated using said second fabrication process; developing a second layout for said integrated circuit, said second layout including location information for each transistor of said integrated circuit within said general pattern, wherein said developing step is performed using the information corresponding to the electronic circuit configured to perform the specified function, information corresponding to a second type integrated circuit fabrication process, and information corresponding to said first type integrated circuit fabrication process, and including the step of adjusting channel widths of transistors in said second layout based upon said differences in characteristics between an integrated circuit fabricated using said first fabrication process and an integrated circuit fabricated using said second fabrication process.
Claim 3
Dependent Claim
48 words
A method as in claim 1 wherein said step of developing said second layout comprises the step of increasing the channel width without causing said channel to be enlarged to a width greater than a distance permitted based upon the location of electrical interconnects extending above said channel.
Claim 4
Dependent Claim
45 words
A method as in claim 1 wherein said integrated circuits comprise N channel transistors and P channel transistors, and said step of developing said second layout comprises the step of adjusting P channel transistor widths and the separate step of adjusting N channel transistor widths.
Claim 5
Dependent Claim
40 words
A method as in claim 1 which further comprises the step of fabricating integrated circuits by using said first layout with said first integrated circuit fabrication process and by using said second layout with said second integrated circuit fabrication process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-08 | 2000-04-08 | 2000-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-08 | 2004-04-08 | 2004-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-08 | 2008-04-08 | 2008-10-08 | $7700.00 | Window Closed / Lapsed |