US4485390A
Expired / Lapsed
US
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Narrow channel FET
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1979-10-01
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Granted: 1984-11-27
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Expires: 1999-10-01
Abstract
Abstract An FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one embodiment, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. The FET is fabricated by forming an oxide mask (e.g., by etching a window in the gate oxide over the device active area); enhancement implanting the substrate through the window (e.g., n-substrate and n-implant for a p-channel FET); enlarging the window width a predetermined distance by etching; and depletion implanting the substrate through the window (p-implant for n-substrate) to a concentration below that of the enhancement implant. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels. This effectively provides an enhancement FET which is in parallel with a depletion FET. The effective channel width of the depletion FET equals the combined width of the two narrow depletion regions and is approximately equal to the difference in width of the two etch-defined windows. The method is applicable to both silicon and metal gate technology, to n-channel and p-channel, and to various combinations of enhancement and/or depletion devices.
Inventors
- 👤 Robert K. Jones
- 👤 Armand J. VAN Velthoven
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/637; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10P; H10P30/00; H10P30/20
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
185 words
In an insulated gate field effect transistor having a channel region having length and width for forming a p-type channel approximately 5 microns wide by approximately 15 microns long in an n-type semiconductor substrate doped to a background concentration of 10 15 cm -3 of phosphorus, the improvement wherein the channel region comprises: a pair of p-type source and drain regions which are formed to a junction depth of about 2 microns at opposite ends of the channel region by boron of concentration 5×10 18 cm -3 ; a relatively wide n-type section extending along the length of the channel region and containing majority carriers with a peak concentration of 5×10 17 cm -3 phosphorus at a depth of about 16 nanometers; and a first relatively narrow p-type section of predetermined width ranging from approximately 0.1 microns to approximately 0.5 microns; the first relatively narrow section extending the length of the channel region at one of opposite sides of the relatively wide section and containing majority carriers doped to a peak concentration of 4×10 17 cm -3 boron at a depth of about 60 nanometers.
Claim 2
Dependent Claim
185 words
In an insulated gate field effect transistor having a channel region having length and width for forming a p-type channel approximately 5 microns wide by approximately 15 microns long in an n-type semiconductor substrate doped to a background concentration of 10 15 cm -3 of phosphorus, the improvement wherein the channel region comprises: a pair of p-type source and drain regions which are formed to a junction depth of about 2 microns at opposite ends of the channel region by boron of concentration 5×10 18 cm -3 ; a relatively wide n-type section extending along the length of the channel region and containing majority carriers with a peak concentration of 5×10 17 cm -3 phosphorus at a depth of about 16 nanometers; and a first relatively narrow p-type section of predetermined width ranging from approximately 0.1 microns to approximately 0.5 microns; the first relatively narrow section extending the length of the channel region at one of opposite sides of the relatively wide section and containing majority carriers doped to a peak concentration of 4×10 17 cm -3 boron at a depth of about 60 nanometers.
Claim 3
Dependent Claim
41 words
The transistor of claim 1, further comprising a second relatively narrow section extending the length of the channel region on the opposite side of the relatively wide section, the second section being substantially identical to the first relatively narrow p-type section.
Claim 4
Dependent Claim
145 words
An improved channel structure for an insulated gate field effect device in which the channel region is formed in a semiconductor material, includes a gate electrode in priximity thereto, and is defined to extend longitudinally, wherein the improvement comprises: a first, longitudinal section of said channel region, lying substantially centered within said channel region and doped to a first impurity concentration; a second, longitudinal section of said channel region, significantly narrower than said first section, lying between said first longitudinal section and one side of said channel region, said second longitudinal section being doped to a second impurity concentration; said first and said second impurity concentrations being characterized in that said second longitudinal section forms a depletion mode channel, and said first longitudinal section forms an enhancement mode channel; and means for biasing the gate electrode such that said first longitudinal section is never inverted.
Claim 5
Dependent Claim
145 words
An improved channel structure for an insulated gate field effect device in which the channel region is formed in a semiconductor material, includes a gate electrode in priximity thereto, and is defined to extend longitudinally, wherein the improvement comprises: a first, longitudinal section of said channel region, lying substantially centered within said channel region and doped to a first impurity concentration; a second, longitudinal section of said channel region, significantly narrower than said first section, lying between said first longitudinal section and one side of said channel region, said second longitudinal section being doped to a second impurity concentration; said first and said second impurity concentrations being characterized in that said second longitudinal section forms a depletion mode channel, and said first longitudinal section forms an enhancement mode channel; and means for biasing the gate electrode such that said first longitudinal section is never inverted.
Claim 6
Dependent Claim
41 words
The structure recited in claim 3, wherein said channel region includes a third longitudinal section, significantly narrower than said first section, lying along the side of said channel region opposite said second longitudinal section and doped to said second impurity concentration.
Claim 7
Dependent Claim
29 words
The structure recited in claim 4, wherein the width of said first longitudinal section exceeds the width of said second longitudinal section by a factor in excess of 5.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-27 | 1988-05-28 | 1988-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-27 | 1992-05-28 | 1992-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-27 | 1996-05-28 | 1996-11-27 | $7700.00 | Window Closed / Lapsed |