US5079717A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and system for compaction-processing mask pattern data of a semiconductor integrated circuit device
Assignee: Mitsubishi Electric Corp
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Filing: 1989-01-18
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Granted: 1992-01-07
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Expires: 2009-01-18
Abstract
Abstract A method for producing a mask pattern for a semiconductor integrated circuit includes dividing the mask pattern data into a plurality of lower level cells and an upper level cell having wiring lines for providing connections between the lower level cells, extracting inter-cell connection information from the mask pattern data, changing the dimensions of the lower level cells by predetermined ratios to conform to a design standard, and changing the wiring lines of the upper level cell to retain the connection between the lower level cells in accordance with the inter-cell connection information extracted.
Inventors
- 👤 Hisaharu Miwa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:28
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
221 words
A method for producing a mask pattern for a semiconductor integrated circuit comprising: reading mask pattern data for the integrated circuit from a storage device of an LSI (large scale integration) mask pattern layout system, the mask pattern data having dimensions according to a first design standard; dividing the mask pattern data into a plurality of units including a plurality of lower level cells having terminal positions and an upper level cell including terminal positions for contacting the terminal positions of the lower level cells and wiring lines running between the terminal positions of the upper level cell to provide a first interconnection network; extracting inter-cell connection information from the mask pattern data; changing the dimensions of the lower level cells according to predetermined ratios to produce compaction-processed lower level cells having terminal positions and dimensions according to a second design standard, the dimensions according to the second design standard being different from the dimensions according to the first design standard; and compaction-processing the upper level cell according to the inter-cell connection information to produce a new upper level cell including terminal positions for contacting the terminal positions of the compaction-processed lower level cells and including wiring lines running between the terminal positions of the new upper level cell to provide a second interconnection network equivalent to the first interconnection network.
Claim 2
Independent Claim
221 words
A method for producing a mask pattern for a semiconductor integrated circuit comprising: reading mask pattern data for the integrated circuit from a storage device of an LSI (large scale integration) mask pattern layout system, the mask pattern data having dimensions according to a first design standard; dividing the mask pattern data into a plurality of units including a plurality of lower level cells having terminal positions and an upper level cell including terminal positions for contacting the terminal positions of the lower level cells and wiring lines running between the terminal positions of the upper level cell to provide a first interconnection network; extracting inter-cell connection information from the mask pattern data; changing the dimensions of the lower level cells according to predetermined ratios to produce compaction-processed lower level cells having terminal positions and dimensions according to a second design standard, the dimensions according to the second design standard being different from the dimensions according to the first design standard; and compaction-processing the upper level cell according to the inter-cell connection information to produce a new upper level cell including terminal positions for contacting the terminal positions of the compaction-processed lower level cells and including wiring lines running between the terminal positions of the new upper level cell to provide a second interconnection network equivalent to the first interconnection network.
Claim 3
Dependent Claim
65 words
A method as recited in claim 1 wherein extracting includes examining the terminal positions of each of the lower level cells and the terminal positions of the upper level cell to identify, for each terminal position of each lower level cell, wiring lines connected to each terminal position of the upper level cell for making contact with each terminal position of each lower level cell.
Claim 4
Dependent Claim
32 words
A method as recited in claim 2 wherein examining includes ascertaining, for each terminal position of the upper level cell, to which of the lower level cells the terminal position is connected.
References Cited (Backward Citations)
US4500963A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-06 | 1995-07-08 | 1996-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-06 | 1999-07-08 | 2000-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-06 | 2003-07-08 | 2004-01-07 | $7700.00 | Window Closed / Lapsed |