Patent US5552732A successfully refreshed from Google Patents.
US5552732A
Expired / Lapsed
US
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High speed divide by 1.5 clock generator
Assignee: Exar Corp
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Filing: 1995-04-25
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Granted: 1996-09-03
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Expires: 2015-04-25
Abstract
Abstract A simple, reliable, divide by 1.5 clock generator is provided. This is done by using a divide by 3 circuit with three gates. The first two gates are clocked by the RLL clock, and the third gate is clocked by the inverse of the RLL clock. The output of the first gate is combined with the RLL clock to provide an output pulse. Another output is produced when the output of the third gate is combined with the inverse of the RLL clock. The combination of these two outputs thus produces a divide by 1.5 clock with a precisely placed rising edge. The output clock is not symmetrical, but the rising edge (or the falling edge on its inverse) is precisely placed at the 1.5 frequency.
Inventors
- 👤 Yihe Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:22
CPC Classifications
H; H03; H03B; H03B19/00; H03K; H03K23/00; H03K23/40; H03K23/50; H03K23/502; H03K23/507
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
159 words
A clock generator circuit for generating a clock edge at a rate of 1.5 times the rate of an input clock, comprising: a first gate having a clock input coupled to said input clock; a second gate having an input coupled to an output of said first gate, and a clock input coupled to said input clock; a third gate having an input coupled to an output of said second gate and a clock input coupled to an inverse of said input clock; combinational logic for providing as a circuit output both a combination of said inverse of said input clock and said first gate output, and a combination of said input clock and said third gate output; and a circuit providing a NOR function having a first input coupled to the output of said first gate, a second input coupled to the output of said second gate, and an output coupled to an input of said first gate.
Claim 2
Dependent Claim
159 words
A clock generator circuit for generating a clock edge at a rate of 1.5 times the rate of an input clock, comprising: a first gate having a clock input coupled to said input clock; a second gate having an input coupled to an output of said first gate, and a clock input coupled to said input clock; a third gate having an input coupled to an output of said second gate and a clock input coupled to an inverse of said input clock; combinational logic for providing as a circuit output both a combination of said inverse of said input clock and said first gate output, and a combination of said input clock and said third gate output; and a circuit providing a NOR function having a first input coupled to the output of said first gate, a second input coupled to the output of said second gate, and an output coupled to an input of said first gate.
Claim 3
Dependent Claim
65 words
The clock generator of claim 1 wherein said combinational logic includes: a first AND gate having a first input coupled to the output of said first gate, and a second input coupled to said inverse of said input clock; and a second AND gate having a first input coupled to the output of said third gate, and a second input coupled to said input clock.
Claim 4
Dependent Claim
48 words
The clock generator of claim 2 wherein said combinational logic further comprises: an OR gate having a first input coupled to an output of said first AND gate, a second input coupled to an output of said second AND gate, and an output producing said output clock edge.
Claim 5
Dependent Claim
13 words
The clock generator of claim 1 wherein said gates are D flip-flop gates.
Claim 6
Dependent Claim
28 words
The clock generator of claim 1 wherein said input clock is an RLL clock and said output clock is a NRZ clock for a disk drive read channel.
Claim 7
Dependent Claim
210 words
A clock generator circuit for generating a clock edge at a rate of 1.5 times the rate of an input clock, comprising: a first gate having a clock input coupled to said input clock; a second gate having an input coupled to an output of said first gate, and a clock input coupled to said input clock; a third gate having an input coupled to an output of said second gate and a clock input coupled to an inverse of said input clock; a NOR gate having a first input coupled to the output of said first gate, a second input coupled to the output of said second gate, and an output coupled to an input of said first gate; a first AND gate having a first input coupled to the output of said first gate, and a second input coupled to said inverse of said input clock; a second AND gate having a first input coupled to the output of said third gate, and a second input coupled to said input clock; and an OR gate having a first input coupled to an output of said first AND gate, a second input coupled to an output of said second AND gate, and an output producing said output clock edge.
Claim 8
Dependent Claim
210 words
A clock generator circuit for generating a clock edge at a rate of 1.5 times the rate of an input clock, comprising: a first gate having a clock input coupled to said input clock; a second gate having an input coupled to an output of said first gate, and a clock input coupled to said input clock; a third gate having an input coupled to an output of said second gate and a clock input coupled to an inverse of said input clock; a NOR gate having a first input coupled to the output of said first gate, a second input coupled to the output of said second gate, and an output coupled to an input of said first gate; a first AND gate having a first input coupled to the output of said first gate, and a second input coupled to said inverse of said input clock; a second AND gate having a first input coupled to the output of said third gate, and a second input coupled to said input clock; and an OR gate having a first input coupled to an output of said first AND gate, a second input coupled to an output of said second AND gate, and an output producing said output clock edge.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-03 | 2000-03-04 | 2000-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-03 | 2004-03-04 | 2004-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-03 | 2008-03-04 | 2008-09-03 | $7700.00 | Window Closed / Lapsed |