US5148050A
Expired / Lapsed
US
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Variable frequency-dividing circuit
Assignee: Toshiba Corp
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Filing: 1991-08-20
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Granted: 1992-09-15
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Expires: 2011-08-20
Abstract
Abstract One output signal of a D flip-flop circuit FF2 is fed via a wiring W1 back to an input terminal of a D flip-flop circuit FF1, while one output signal of a D flip-flop circuit FF3 is fed via a wiring W2 back to another input terminal of the D flip-flop circuit FF1. One output signal of the D flip-flop circuit FF1 is supplied to an edge-trigger type flip-flop circuit FF4. A NAND circuit NA generates a reset signal in accordance with the output signal of the edge-trigger type flip-flop circuit FF4 and a frequency-dividing switching control signal which changes the frequency-dividing ratio, and sends the reset signal to the D flip-flop circuit FF3. These D flip-flop circuits FF1, FF2, FF3 and FF4 frequency-divide a clock signal by an odd number or an even number. The D flip-flop circuits FF1, FF2, FF3 and FF4 each comprise multiple NOR gates, which each include field-effect transistors. The current-driving performance of the field-effect transistors constituting the NOR gates to which feedback circuits, such as the wirings W1 and W2, are connected as a load, is set almost two to four times that of the field-effect transistors constituting those NOR gates where no feedback circuits are connected.
Inventors
- 👤 Nobuo Koide
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:37
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/667
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
364 words
A variable frequency-dividing circuit comprising: a first flip-flop circuit for sequentially generating input signals in response to a clock signal, said first flip-flop circuit including first and second gate circuits responsive to said input signals and third and fourth gate circuits for generating signals from said first and second gate circuits as opposite signals in response to a clock signal, said first to fourth gate circuits each having field-effect transistors; a second flip-flop circuit including fifth and sixth gate circuits responsive to said opposite signals, and seventh and eighth gate circuits for generating signals from said fifth and sixth gate circuits in response to a clock signal, said fifth to eighth gate circuits each having field-effect transistors; a third flip-flop circuit including ninth and tenth gate circuits responsive to opposite signals from said seventh and eighth gate circuits, and eleventh and twelfth gate circuits for generating signals from said ninth and tenth gate circuits in response to a clock signal, said ninth to twelfth gate circuits each having field-effect transistors; first means for feeding a signal from said seventh gate circuit to said second gate circuit; second means for feeding a signal from said eleventh gate circuit to said second gate circuit; a fourth flip-flop circuit including a thirteenth gate circuit responsive to a signal from said fourth gate circuit, and a fourteenth gate circuit for frequency-dividing a signal from said thirteenth gate circuit and generating said frequency-divided signal, said thirteenth and fourteenth gate circuits each having field-effect transistors; and third means for generating a reset signal in accordance with said signal from said fourteenth gate circuit and a signal for changing a frequency-dividing ratio, and supplying said reset signal to said eleventh gate circuit, wherein field-effect transistors constituting said fourth, seventh, eleventh and fourteenth gate circuits have wider channel widths than channel widths of said field-effect transistors constituting said first, second, third, fifth, sixth, eighth, ninth, tenth, twelfth and thirteenth gate circuits, and said field-effect transistors constituting said fourth, seventh, eleventh and fourteenth gate circuits have a current-driving performance two to four times that of said field-effect transistors constituting said first, second, third, fifth, sixth, eighth, ninth, tenth, twelfth and thirteenth gate circuits.
Claim 2
Dependent Claim
364 words
A variable frequency-dividing circuit comprising: a first flip-flop circuit for sequentially generating input signals in response to a clock signal, said first flip-flop circuit including first and second gate circuits responsive to said input signals and third and fourth gate circuits for generating signals from said first and second gate circuits as opposite signals in response to a clock signal, said first to fourth gate circuits each having field-effect transistors; a second flip-flop circuit including fifth and sixth gate circuits responsive to said opposite signals, and seventh and eighth gate circuits for generating signals from said fifth and sixth gate circuits in response to a clock signal, said fifth to eighth gate circuits each having field-effect transistors; a third flip-flop circuit including ninth and tenth gate circuits responsive to opposite signals from said seventh and eighth gate circuits, and eleventh and twelfth gate circuits for generating signals from said ninth and tenth gate circuits in response to a clock signal, said ninth to twelfth gate circuits each having field-effect transistors; first means for feeding a signal from said seventh gate circuit to said second gate circuit; second means for feeding a signal from said eleventh gate circuit to said second gate circuit; a fourth flip-flop circuit including a thirteenth gate circuit responsive to a signal from said fourth gate circuit, and a fourteenth gate circuit for frequency-dividing a signal from said thirteenth gate circuit and generating said frequency-divided signal, said thirteenth and fourteenth gate circuits each having field-effect transistors; and third means for generating a reset signal in accordance with said signal from said fourteenth gate circuit and a signal for changing a frequency-dividing ratio, and supplying said reset signal to said eleventh gate circuit, wherein field-effect transistors constituting said fourth, seventh, eleventh and fourteenth gate circuits have wider channel widths than channel widths of said field-effect transistors constituting said first, second, third, fifth, sixth, eighth, ninth, tenth, twelfth and thirteenth gate circuits, and said field-effect transistors constituting said fourth, seventh, eleventh and fourteenth gate circuits have a current-driving performance two to four times that of said field-effect transistors constituting said first, second, third, fifth, sixth, eighth, ninth, tenth, twelfth and thirteenth gate circuits.
Claim 3
Dependent Claim
45 words
A circuit according to claim 1, wherein said field-effect transistors constituting said fourth, seventh, eleventh and fourteenth gate circuits have a current-driving performance three times that of said field-effect transistors constituting said first, second, third, fifth, sixth, eighth, ninth, tenth, twelfth and thirteenth gate circuits.
Claim 4
Dependent Claim
45 words
A circuit according to claim 1, wherein said field-effect transistors constituting said fourth, seventh, eleventh and fourteenth gate circuits have a channel width three times that of said field-effect transistors constituting said first, second, third, fifth, sixth, eighth, ninth, tenth, twelfth and thirteenth gate circuits.
Claim 5
Dependent Claim
21 words
A circuit according to claim 1, wherein said first to third flip-flop circuits each comprise a master-slave type D flip-flop circuit.
Claim 6
Dependent Claim
17 words
A circuit according to claim 1, wherein said fourth flip-flop circuit comprises an edge-trigger type flip-flop circuit.
Claim 7
Dependent Claim
18 words
A circuit according to claim 1, wherein said first and second means are each constituted of a wiring.
Claim 8
Dependent Claim
128 words
A variable frequency-dividing circuit comprising: a frequency-dividing circuit for frequency-dividing an input signal according to a clock signal and for generating a frequency-divided signal, said frequency-dividing circuit including a first gate circuit responsive to said input signal, the first gate circuit including an output stage having a field effect transistor having a first channel width and a first current-driving performance, and a second gate circuit for generating said frequency-divided signal, the second gate circuit including an output stage having a field effect transistor having a second channel width greater than the first channel width and a second current-driving performance two to four times greater than the first current driving performance; and feedback circuit means for feeding a signal from said second gate circuit to said first gate circuit.
Claim 9
Dependent Claim
128 words
A variable frequency-dividing circuit comprising: a frequency-dividing circuit for frequency-dividing an input signal according to a clock signal and for generating a frequency-divided signal, said frequency-dividing circuit including a first gate circuit responsive to said input signal, the first gate circuit including an output stage having a field effect transistor having a first channel width and a first current-driving performance, and a second gate circuit for generating said frequency-divided signal, the second gate circuit including an output stage having a field effect transistor having a second channel width greater than the first channel width and a second current-driving performance two to four times greater than the first current driving performance; and feedback circuit means for feeding a signal from said second gate circuit to said first gate circuit.
Claim 10
Dependent Claim
20 words
A circuit according to claim 7, wherein said second current-driving performance is three times greater than said first current-driving performance.
Claim 11
Dependent Claim
20 words
A circuit according to claim 7, wherein said second channel width is three times greater than said first channel width.
Claim 12
Dependent Claim
15 words
A circuit according to claim 7, wherein said circuit means is constituted of a wiring.
Claim 13
Dependent Claim
21 words
A circuit according to claim 7, wherein said second gate circuit includes a plurality of metal schottky field-effect transistor having GaAs.
Claim 14
Dependent Claim
21 words
A circuit according to claim 11, wherein said first gate circuit includes a plurality of metal schottky field-effect transistor having GaAs.
Claim 15
Dependent Claim
158 words
A variable frequency-dividing circuit comprising: a first flip-flop circuit, responsive to a data signal and to a clock signal, including a first gate circuit for generating a first signal, the first gate circuit including an output stage having a field effect transistor having a first channel width, and a second gate circuit for generating a second signal, the second gate circuit including an output stage having a field effect transistor having a second channel width greater than the first channel width; and a second flip-flop circuit, responsive to the first signal and to the second signal, including a third gate circuit for generating a third signal, the third gate circuit including an output stage having a field effect transistor having a third channel width and a fourth gate circuit for generating the data signal, the fourth gate circuit including an output stage having a field effect transistor having a fourth channel width greater than the third channel width.
Claim 16
Dependent Claim
158 words
A variable frequency-dividing circuit comprising: a first flip-flop circuit, responsive to a data signal and to a clock signal, including a first gate circuit for generating a first signal, the first gate circuit including an output stage having a field effect transistor having a first channel width, and a second gate circuit for generating a second signal, the second gate circuit including an output stage having a field effect transistor having a second channel width greater than the first channel width; and a second flip-flop circuit, responsive to the first signal and to the second signal, including a third gate circuit for generating a third signal, the third gate circuit including an output stage having a field effect transistor having a third channel width and a fourth gate circuit for generating the data signal, the fourth gate circuit including an output stage having a field effect transistor having a fourth channel width greater than the third channel width.
Claim 17
Dependent Claim
21 words
A circuit according to claim 13, wherein said first and second flip-flop circuits each comprise a master-slave type D flip-flop circuit.
Claim 18
Dependent Claim
18 words
A circuit according to claim 13, further including an edge-trigger type flip-flop circuit responsive to the second signal.
Claim 19
Dependent Claim
20 words
A circuit according to claim 13, wherein the second channel width is three times greater than the first channel width.
Claim 20
Dependent Claim
20 words
A circuit according to claim 13, wherein the fourth channel width is three times greater than the third channel width.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |