US4902909A
Expired / Lapsed
US
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Flip-flop arrangement for a divide-by-2 frequency divider comprising master-slave type memory elements
Assignee: US Philips Corp
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Filing: 1989-02-21
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Granted: 1990-02-20
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Expires: 2009-02-21
Abstract
Abstract A flip-flop (40) for a divide-by-2 frequency divider having a first stage (50) formed by two master-slave-type memory elements (10a, 10b) each having a two-input NOR gate (20a, 20b), and by a second stage (60) with 2 NOR gates (61, 62) connected as an RS flip-flop. The memory elements (10a, 10b) also include an enhancement-type MESFET transistor (30a, 30b), the gates (Ga, Gb) and the drains (Da, Db) of said transistors (30a, 30b) being coupled to the respective inputs of the NOR-gates (20a, 20b).
Inventors
- 👤 Bernard Chantepie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:18
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
117 words
Flip-flop arrangement for halving a frequency of a signal received on an input terminal, comprising: a RS-flip-flop with a first and a second logic gate that have their first gate inputs mutually intercoupled to their gate outputs; a third logic gate and a fourth logic gate having respective gate outputs coupled to a second gate input of the first and the second logic gate, respectively, and having first gate inputs coupled to a gate output of the second and first logic gate, respectively, via a conduction path of a first and a second switch, respectively the second gate inputs of the third and fourth logic gates and control inputs of switches being coupled to said input terminal.
Claim 2
Dependent Claim
117 words
Flip-flop arrangement for halving a frequency of a signal received on an input terminal, comprising: a RS-flip-flop with a first and a second logic gate that have their first gate inputs mutually intercoupled to their gate outputs; a third logic gate and a fourth logic gate having respective gate outputs coupled to a second gate input of the first and the second logic gate, respectively, and having first gate inputs coupled to a gate output of the second and first logic gate, respectively, via a conduction path of a first and a second switch, respectively the second gate inputs of the third and fourth logic gates and control inputs of switches being coupled to said input terminal.
Claim 3
Dependent Claim
24 words
Flip-flop arrangement as claimed in claim 1, wherein the logic gates each comprise a NOR-gate, the switches each comprising an enhancement field effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |