Programmable digital frequency divider for synthesizing signals at desired frequency

Claim 2

A programmable digital frequency divider comprising: a programmable binary counter respective of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; and a binary code converter comprising a plurality of input terminals to which is applied an M-bit input binary signal, a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit connected between said input and output terminals for converting said M-bit input binary signal into an N-bit output binary signal for application to said output terminals, where N equals an integral multiple of M minus an error compensating number which causes the frequency of said output pulses to vary substantially linearly as a function of discrete variations of said input binary signal.

Claim 3

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises a plurality of inverters connected to said input terminals, a plurality of AND gates connected to the outputs of said inverters and said input terminals, and a plurality of OR gates connected to receive output signals from said AND gates, the output terminals of said OR gates being connected respectively to said output terminals of said binary code converter.

Claim 4

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises a plurality of inverters connected to said input terminals, a plurality of AND gates connected to the outputs of said inverters and said input terminals, and a plurality of OR gates connected to receive output signals from said AND gates, the output terminals of said OR gates being connected respectively to said output terminals of said binary code converter.

Claim 5

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; and a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit comprises first means for counting said input pulses to increment the binary states of said output terminals, means for eliminating said input pulse at predetermined intervals, and second means for counting said input pulses to disable said first counting means in response to a count determined by said binary states of said control terminals.

Claim 6

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; and a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit comprises first means for counting said input pulses to increment the binary states of said output terminals, means for eliminating said input pulse at predetermined intervals, and second means for counting said input pulses to disable said first counting means in response to a count determined by said binary states of said control terminals.

Claim 7

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit comprises a counter having a plurality of counter states connected respectively to said output terminals of said binary code converter, means connected to said input terminals of said binary code converter for enabling said counter to count said input pulses for a period of time depending on the binary states of said input terminals, and means for eliminating an input pulse to be counted by said counter at predetermined intervals.

Claim 8

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit comprises a counter having a plurality of counter states connected respectively to said output terminals of said binary code converter, means connected to said input terminals of said binary code converter for enabling said counter to count said input pulses for a period of time depending on the binary states of said input terminals, and means for eliminating an input pulse to be counted by said counter at predetermined intervals.

Claim 9

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit of said binary code converter comprises a first binary counter having a plurality of counter stages for receiving said input pulses, a plurality of coincidence gates connected to the counter stages of said first binary counter for generating a coincidence output in response to each of a plurality of sets of predetermined binary states of the counter stages of said first binary counter, a second binary counter having a plurality of counter stages connected respectively to said output terminals, means connected to said input terminals and to said counter stages of said first binary counter for enabling said second binary counter to receive said input pulses, and means responsive to said coincidence output for eliminating an input pulse to be received by said second binary counter.

Claim 10

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit of said binary code converter comprises a first binary counter having a plurality of counter stages for receiving said input pulses, a plurality of coincidence gates connected to the counter stages of said first binary counter for generating a coincidence output in response to each of a plurality of sets of predetermined binary states of the counter stages of said first binary counter, a second binary counter having a plurality of counter stages connected respectively to said output terminals, means connected to said input terminals and to said counter stages of said first binary counter for enabling said second binary counter to receive said input pulses, and means responsive to said coincidence output for eliminating an input pulse to be received by said second binary counter.

Claim 11

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit of said binary code converter comprises: a first binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" input pulses and a second group of counter stages responsive to the output pulse of said first group counter stages; means for detecting noncoincidence between the binary states of the input terminals of said binary code converter and the binary states of the second group counter stages of said first binary counter to enable said first group counter stages of said first binary counter to receive said input pulses and detecting coincidence therebetween to disable said first group counter stages of said first counter; a second binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" input pulses and a second group of counter stages responsive to the output pulses of said first group counter stages of said first and second binary counters, the output terminals of all of said counter stages of said second counter being connected respectively to the output terminals of said binary code converter; a third binary counter for generating an output pulse in response to a count of "m-1" input pulses for eliminating an input pulse to be received by said first group counter stages of said second binary counter; and means including a plurality of coincidence gates connected respectively to the second group counter stages of said first binary counter to establish a plurality of sets of binary conditions to develop an output pulse in each of said coincidence gates in response to said second group counter stages of said first binary counter satisfying said established set of binary conditions for enabling said third binary counter and said first group counter stages of said second binary counter to receive said input pulses and disabling said second group counter stages of said second binary counter.

Claim 12

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit of said binary code converter comprises: a first binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" input pulses and a second group of counter stages responsive to the output pulse of said first group counter stages; means for detecting noncoincidence between the binary states of the input terminals of said binary code converter and the binary states of the second group counter stages of said first binary counter to enable said first group counter stages of said first binary counter to receive said input pulses and detecting coincidence therebetween to disable said first group counter stages of said first counter; a second binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" input pulses and a second group of counter stages responsive to the output pulses of said first group counter stages of said first and second binary counters, the output terminals of all of said counter stages of said second counter being connected respectively to the output terminals of said binary code converter; a third binary counter for generating an output pulse in response to a count of "m-1" input pulses for eliminating an input pulse to be received by said first group counter stages of said second binary counter; and means including a plurality of coincidence gates connected respectively to the second group counter stages of said first binary counter to establish a plurality of sets of binary conditions to develop an output pulse in each of said coincidence gates in response to said second group counter stages of said first binary counter satisfying said established set of binary conditions for enabling said third binary counter and said first group counter stages of said second binary counter to receive said input pulses and disabling said second group counter stages of said second binary counter.

Claim 13

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; and a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals.

Claim 14

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; and a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals.

Claim 15

A digital frequency synthesizer as claimed in claim 7, wherein the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number.

Claim 16

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit of said binary code converter comprises a plurality of inverters connected to said input terminals, a plurality of AND gates connected to the outputs of said inverters and said input terminals, and a plurality of OR gates connected to receive output signals from said AND gates, the output terminals of said OR gates being connected respectively to said output terminals of said binary code converter.

Claim 17

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit of said binary code converter comprises a plurality of inverters connected to said input terminals, a plurality of AND gates connected to the outputs of said inverters and said input terminals, and a plurality of OR gates connected to receive output signals from said AND gates, the output terminals of said OR gates being connected respectively to said output terminals of said binary code converter.

Claim 18

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit comprises first means for counting said clock pulses to increment the binary states of said outputs terminals, means for eliminating a said input pulse at predetermined intervals, and second means for counting said clock pulses to disable said first counting means in response to a count determined by said binary states of said control terminals.

Claim 19

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit comprises first means for counting said clock pulses to increment the binary states of said outputs terminals, means for eliminating a said input pulse at predetermined intervals, and second means for counting said clock pulses to disable said first counting means in response to a count determined by said binary states of said control terminals.

Claim 20

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit comprises a counter having a plurality of counter stages connected respectively to said output terminals of said binary code converter, means connected to said input terminals of said binary code converter for enabling said counter to count said clock pulses for a period of time depending on the binary states of said input terminals, and means for eliminating a clock pulse to be counter by said counter at predetermined intervals.

Claim 21

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit comprises a counter having a plurality of counter stages connected respectively to said output terminals of said binary code converter, means connected to said input terminals of said binary code converter for enabling said counter to count said clock pulses for a period of time depending on the binary states of said input terminals, and means for eliminating a clock pulse to be counter by said counter at predetermined intervals.

Claim 22

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit of said binary code converter comprises a first binary counter having a plurality of counter stages for receiving said clock pulses, a plurality of coincidence gates connected to the counter stages of said first binary counter for generating a coincidence output in response to each of a plurality of sets of predetermined binary states of the counter stages of said first binary counter, a second binary counter having a plurality of counter stages connected respectively to said output terminals, means connected to said input terminals and to said counter stages of said first binary counter for enabling said second binary counter to receive said clock pulses, and means responsive to said coincidence output for eliminating a clock pulse to be received by said second binary counter.

Claim 23

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic circuit of said binary code converter comprises a first binary counter having a plurality of counter stages for receiving said clock pulses, a plurality of coincidence gates connected to the counter stages of said first binary counter for generating a coincidence output in response to each of a plurality of sets of predetermined binary states of the counter stages of said first binary counter, a second binary counter having a plurality of counter stages connected respectively to said output terminals, means connected to said input terminals and to said counter stages of said first binary counter for enabling said second binary counter to receive said clock pulses, and means responsive to said coincidence output for eliminating a clock pulse to be received by said second binary counter.

Claim 24

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic cicuit of said binary code converter comprises: a first binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" clock pulses and a second group of counter stages responsive to the output pulse of said first group counter stages; means for detecting noncoincidence between the binary states of the input terminals of said binary code converter and the binary states of the second group counter stages of said first binary counter to enable said first group counter stages of said first binary counter to receive said clock pulses and detecting coincidence therebetween to disable said first group counter stages of said first counter; a second binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" clock pulses and a second group of counter stages responsive to the output pulses of said first group counter stages of said first and second binary counters, the output terminals of all of said counter stages of said second counter being connected respectively to the output terminals of said binary code converter; a third binary counter for generating an output pulse in response to a count of "m-1" clock pulses for eliminating a clock pulse to be received by said first group counter stages of said second binary counter; and means including a plurality of coincidence gates connected respectively to the second group counter stages of said first binary counter to establish a plurality of sets of binary conditions to develop an output pulse in each of said coincidence gates in response to said second group counter stages of said first binary counter satisfying said established set of binary conditions for enabling said third binary counter and said first group counter stages of said second binary counter to receive said clock pulses and disabling said second group counter stages of said second binary counter.

Claim 25

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; and wherein said logic cicuit of said binary code converter comprises: a first binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" clock pulses and a second group of counter stages responsive to the output pulse of said first group counter stages; means for detecting noncoincidence between the binary states of the input terminals of said binary code converter and the binary states of the second group counter stages of said first binary counter to enable said first group counter stages of said first binary counter to receive said clock pulses and detecting coincidence therebetween to disable said first group counter stages of said first counter; a second binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" clock pulses and a second group of counter stages responsive to the output pulses of said first group counter stages of said first and second binary counters, the output terminals of all of said counter stages of said second counter being connected respectively to the output terminals of said binary code converter; a third binary counter for generating an output pulse in response to a count of "m-1" clock pulses for eliminating a clock pulse to be received by said first group counter stages of said second binary counter; and means including a plurality of coincidence gates connected respectively to the second group counter stages of said first binary counter to establish a plurality of sets of binary conditions to develop an output pulse in each of said coincidence gates in response to said second group counter stages of said first binary counter satisfying said established set of binary conditions for enabling said third binary counter and said first group counter stages of said second binary counter to receive said clock pulses and disabling said second group counter stages of said second binary counter.

Claim 26

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit comprises first means for counting said input pulses to increment the binary states of said output terminals, means for eliminating said input pulse at predetermined intervals, and second means for counting said input pulses to disable said first counting means in response to a count determined by said binary states of said control terminals.

Claim 27

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit comprises first means for counting said input pulses to increment the binary states of said output terminals, means for eliminating said input pulse at predetermined intervals, and second means for counting said input pulses to disable said first counting means in response to a count determined by said binary states of said control terminals.

Claim 28

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit comprises a counter having a plurality of counter stages connected respectively to said output terminals of said binary code converter, means connected to said input terminals of said binary code converter for enabling said counter to count said input pulses for a period of time depending on the binary states of said input terminals, and means for eliminating an input pulse to be counted by said counter at predetermined intervals.

Claim 29

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit comprises a counter having a plurality of counter stages connected respectively to said output terminals of said binary code converter, means connected to said input terminals of said binary code converter for enabling said counter to count said input pulses for a period of time depending on the binary states of said input terminals, and means for eliminating an input pulse to be counted by said counter at predetermined intervals.

Claim 30

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises a first binary counter having a plurality of counter stages for receiving said input pulses, a plurality of coincidence gates connected to the counter stages of said first binary counter for generating a coincidence output in response to each of a plurality of sets of predetermined binary states of the counter stages of said first binary counter, a second binary counter having a plurality of counter stages connected respectively to said output terminals, means connected to said input terminals and to said counter stages of said first binary counter for enabling said second binary counter to receive said input pulses, and means responsive to said coincidence output for eliminating an input pulse to be received by said second binary counter.

Claim 31

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises a first binary counter having a plurality of counter stages for receiving said input pulses, a plurality of coincidence gates connected to the counter stages of said first binary counter for generating a coincidence output in response to each of a plurality of sets of predetermined binary states of the counter stages of said first binary counter, a second binary counter having a plurality of counter stages connected respectively to said output terminals, means connected to said input terminals and to said counter stages of said first binary counter for enabling said second binary counter to receive said input pulses, and means responsive to said coincidence output for eliminating an input pulse to be received by said second binary counter.

Claim 32

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises: a first binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" input pulses and a second group of counter stages responsive to the output pulse of said first group counter stages; means for detecting noncoincidence between the binary states of the input terminals of said binary code converter and the binary states of the second group counter stages of said first binary counter to enable said first group counter stages of said fist binary counter to receive said input pulses and detecting coincidence therebetween to disable said first group counter stages of said first counter; a second binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" input pulses and a second group of counter stages responsive to the output pulses of said first group counter stages of said first and second binary counters, the output terminals of all of said counter stages of said second counter being connected respectively to the output terminals of said binary code converter; a third binary counter for generating an output pulse in response to a count of "m-1" input pulses for eliminating an input pulse to be received by said first group counter stages of said second binary counter; and means including a plurality of coincidence gates connected respectively to the second group counter stages of said first binary counter to establish a plurality of sets of binary conditions to develop an output pulse in each of said coincidence gates in response to said second group counter stages of said first binary counter satisfying said established set of binary conditions for enabling said third binary counter and said first group counter stages of said second binary counter to receive said input pulses and disabling said second group counter stages of said second binary counter.

Claim 33

A programmable digital frequency divider comprising: a programmable binary counter receptive of input pulses from a pulse source and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding normal binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises: a first binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" input pulses and a second group of counter stages responsive to the output pulse of said first group counter stages; means for detecting noncoincidence between the binary states of the input terminals of said binary code converter and the binary states of the second group counter stages of said first binary counter to enable said first group counter stages of said fist binary counter to receive said input pulses and detecting coincidence therebetween to disable said first group counter stages of said first counter; a second binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" input pulses and a second group of counter stages responsive to the output pulses of said first group counter stages of said first and second binary counters, the output terminals of all of said counter stages of said second counter being connected respectively to the output terminals of said binary code converter; a third binary counter for generating an output pulse in response to a count of "m-1" input pulses for eliminating an input pulse to be received by said first group counter stages of said second binary counter; and means including a plurality of coincidence gates connected respectively to the second group counter stages of said first binary counter to establish a plurality of sets of binary conditions to develop an output pulse in each of said coincidence gates in response to said second group counter stages of said first binary counter satisfying said established set of binary conditions for enabling said third binary counter and said first group counter stages of said second binary counter to receive said input pulses and disabling said second group counter stages of said second binary counter.

Claim 34

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises a plurality of inverters connected to said input terminals, a plurality of AND gates connected to the outputs of said inverters and said input terminals, and a plurality of OR gates connected to receive output signals from said AND gates, the output terminals of said OR gates being connected respectively to said output terminals of said binary code converter.

Claim 35

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises a plurality of inverters connected to said input terminals, a plurality of AND gates connected to the outputs of said inverters and said input terminals, and a plurality of OR gates connected to receive output signals from said AND gates, the output terminals of said OR gates being connected respectively to said output terminals of said binary code converter.

Claim 36

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral mulitple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit comprises first means for counting said clock pulses to increment the binary states of said outputs terminals, means for eliminating a said input pulse at predetermined intervals, and second means for counting said clock pulses to disable said first counting means in response to a count determined by said binary states of said control terminals.

Claim 37

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral mulitple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit comprises first means for counting said clock pulses to increment the binary states of said outputs terminals, means for eliminating a said input pulse at predetermined intervals, and second means for counting said clock pulses to disable said first counting means in response to a count determined by said binary states of said control terminals.

Claim 38

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit comprises a counter having a plurality of counter stages connected respectively to said output terminals of said binary code converter, means connected to said input terminals of said binary code converter for enabling said counter to count said clock pulses for a period of time depending on the binary states of said input terminals, and means for eliminating a clock pulse to be counter by said counter at predetermined intervals.

Claim 39

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit comprises a counter having a plurality of counter stages connected respectively to said output terminals of said binary code converter, means connected to said input terminals of said binary code converter for enabling said counter to count said clock pulses for a period of time depending on the binary states of said input terminals, and means for eliminating a clock pulse to be counter by said counter at predetermined intervals.

Claim 40

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises a first binary counter having a plurality of counter stages for receiving said clock pulses, a plurality of coincidence gates connected to the counter stages of said first binary counter for generating a coincidence output in response to each of a plurality of sets of predetermined binary states of the counter stages of said first binary counter, a second binary counter having a plurality of counter stages connected respectively to said output terminals, means connected to said input terminals and to said counter stages of said first binary counter for enabling said second binary counter to receive said clock pulses, and means responsive to said coincidence output for eliminating a clock pulse to be received by said second binary counter.

Claim 41

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises a first binary counter having a plurality of counter stages for receiving said clock pulses, a plurality of coincidence gates connected to the counter stages of said first binary counter for generating a coincidence output in response to each of a plurality of sets of predetermined binary states of the counter stages of said first binary counter, a second binary counter having a plurality of counter stages connected respectively to said output terminals, means connected to said input terminals and to said counter stages of said first binary counter for enabling said second binary counter to receive said clock pulses, and means responsive to said coincidence output for eliminating a clock pulse to be received by said second binary counter.

Claim 42

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises: a first binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" clock pulses and a second group of counter stages responsive to the output pulse of said first group counter stages; means for detecting noncoincidence between the binary states of the input terminals of said binary code converter and the binary states of the second group counter stages of said first binary counter to enable said first group counter stages of said first binary counter to receive said clock pulses and detecting coincidence therebetween to disable said first group counter stages of said first counter; a second binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" clock pulses and a second group of counter stages responsive to the output pulses of said first group counter stages of said first and second binary counters, the output terminals of all of said counter stages of said second counter being connected respectively to the output terminals of said binary code converter; a third binary counter for generating an output pulse in response to a count of "m-1" clock pulses for eliminating a clock pulse to be received by said first group counter stages of said second binary counter; and means including a plurality of coincidence gates connected respectively to the second group counter stages of said first binary counter to establish a plurality of sets of binary conditions to develop an output pulse in each of said coincidence gates in response to said second group counter stages of said first binary counter satisfying said established set of binary conditions for enabling said third binary counter and said first group counter stages of said second binary counter to receive said clock pulses and disabling said second group counter stages of said second binary counter.

Claim 43

A digital frequency synthesizer comprising: a source of clock pulses; a programmable binary counter receptive of said clock pulses and having a plurality of control terminals for generating output pulses at a frequency variable in accordance with a set of binary states of said control terminals; a binary code converter comprising a plurality of input terminals and a plurality of output terminals connected to said control terminals of said programmable counter, and a logic circuit for converting a set of binary states of said input terminals supplied in the form of a normal binary number system into a set of binary states of said output terminals in the form of a modified binary number system for conditioning said programmable counter such that the frequency of said output pulses is substantially linearly variable as a function of discrete variations of the binary states of said input terminals; wherein the modified binary number is an integral multiple of the corresponding input binary number minus error compensating binary digits, the number of said compensating binary digits varying in dependence on the particular binary number; and further wherein said logic circuit of said binary code converter comprises: a first binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" clock pulses and a second group of counter stages responsive to the output pulse of said first group counter stages; means for detecting noncoincidence between the binary states of the input terminals of said binary code converter and the binary states of the second group counter stages of said first binary counter to enable said first group counter stages of said first binary counter to receive said clock pulses and detecting coincidence therebetween to disable said first group counter stages of said first counter; a second binary counter having a first group of counter stages for generating an output pulse in response to a count of "m" clock pulses and a second group of counter stages responsive to the output pulses of said first group counter stages of said first and second binary counters, the output terminals of all of said counter stages of said second counter being connected respectively to the output terminals of said binary code converter; a third binary counter for generating an output pulse in response to a count of "m-1" clock pulses for eliminating a clock pulse to be received by said first group counter stages of said second binary counter; and means including a plurality of coincidence gates connected respectively to the second group counter stages of said first binary counter to establish a plurality of sets of binary conditions to develop an output pulse in each of said coincidence gates in response to said second group counter stages of said first binary counter satisfying said established set of binary conditions for enabling said third binary counter and said first group counter stages of said second binary counter to receive said clock pulses and disabling said second group counter stages of said second binary counter.