US4443887A
Expired / Lapsed
US
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Frequency-dividing circuit
Assignee: Victor Company of Japan Ltd
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Filing: 1981-06-12
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Granted: 1984-04-17
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Expires: 2001-06-12
Abstract
Abstract A frequency-dividing circuit comprises an asynchronous counter having a plurality of one-half frequency-dividers connected in series in a plurality of stages in which a master clock signal is applied to an input terminal of the initial stage, for asynchronously producing output signals of each of the one-half frequency-dividers, where the asynchronous counter is set with a preset data n (n is an integer) which is preset according to a desired frequency-dividing ratio when a load pulse is applied, a coincidence detection circuit for detecting the coincidence of a plurality of outputs supplied from the asynchronous counter, and a frequency-divided output signal and load pulse generation circuit supplied with the master clock signal and an output signal of the coincidence detection circuit, for generating a frequency-divided output signal and a load pulse. The frequency-divided output signal and load pulse generation circuit supplies a load pulse to the asynchronous counter.
Inventors
- 👤 Takami Shiramizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:33
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/58; H03K21/00; H03K21/08; H03K21/12; H03K23/64; H03K23/66; H03K23/665
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
301 words
A frequency-dividing circuit comprising: asynchronous counter means having a plurality of one-half frequency-dividers connected in series in a plurality of stages in which a master clock signal is applied to an input terminal of the initial stage, for asynchronously producing output signals of each one-half frequency-dividers, said asynchronous counter means being set with a preset data n (n is an integer) which is preset according to a desired frequency-dividing ratio when applied with a load pulse; an AND-circuit for detecting the coincidence of a plurality of outputs supplied from said asynchronous counter means; and frequency-divided output signal and load pulse generation means supplied with said master clock signal and an output signal of said AND-circuit, for generating a frequency-divided output signal and a load pulse, said frequency-divided output signal and load pulse generation means supplying a load pulse to said asynchronous counter means, said frequency-divided output signal and load pulse generation means comprising a shifting circuit supplied with an output of said AND-circuit and the master clock signal, for shifting the signal supplied thereto by a predetermined quantity by being synchronized with the output of said AND-circuit and the master clock signal, a trigger-type flip-flop circuit for producing a frequency-divided output signal by reversing state in response to a final shifted output signal obtained from said shifting circuit, and a load pulse generation circuit supplied with the output signal of said shifting circuit and the frequency-divided output signal of said trigger-type flip-flop circuit, for producing the load pulse, said shifting circuit having a first shift register supplied with the output of said AND-circuit and the master clock signal, and a second shift register supplied with an output of said first shift register and the master clock signal, said trigger-type flip-flop circuit being supplied with an output of said second shift register.
Claim 2
Dependent Claim
301 words
A frequency-dividing circuit comprising: asynchronous counter means having a plurality of one-half frequency-dividers connected in series in a plurality of stages in which a master clock signal is applied to an input terminal of the initial stage, for asynchronously producing output signals of each one-half frequency-dividers, said asynchronous counter means being set with a preset data n (n is an integer) which is preset according to a desired frequency-dividing ratio when applied with a load pulse; an AND-circuit for detecting the coincidence of a plurality of outputs supplied from said asynchronous counter means; and frequency-divided output signal and load pulse generation means supplied with said master clock signal and an output signal of said AND-circuit, for generating a frequency-divided output signal and a load pulse, said frequency-divided output signal and load pulse generation means supplying a load pulse to said asynchronous counter means, said frequency-divided output signal and load pulse generation means comprising a shifting circuit supplied with an output of said AND-circuit and the master clock signal, for shifting the signal supplied thereto by a predetermined quantity by being synchronized with the output of said AND-circuit and the master clock signal, a trigger-type flip-flop circuit for producing a frequency-divided output signal by reversing state in response to a final shifted output signal obtained from said shifting circuit, and a load pulse generation circuit supplied with the output signal of said shifting circuit and the frequency-divided output signal of said trigger-type flip-flop circuit, for producing the load pulse, said shifting circuit having a first shift register supplied with the output of said AND-circuit and the master clock signal, and a second shift register supplied with an output of said first shift register and the master clock signal, said trigger-type flip-flop circuit being supplied with an output of said second shift register.
Claim 3
Dependent Claim
116 words
A frequency-dividing circuit as claimed in claim 1 in which said load pulse generation circuit has an odd/even number switching terminal to which a different signal is applied according to whether a denominator N (N is an integer) of the frequency-dividing ratio 1/N is an odd or an even number, and a reset signal input terminal connected to said shifting circuit and said trigger-type flip-flop circuit, said reset signal input terminal being supplied with a reset signal when said shifting circuit and said trigger-type flip-flop circuit are to be reset, said frequency-dividing circuit being switched over to produce an odd or even frequency-divided output signal according to the signal applied to said odd/even number switching terminal.
Claim 4
Dependent Claim
119 words
A frequency-dividing circuit as claimed in claim 2 in which said load pulse generation circuit comprises: a first AND-gate supplied with an inverted output signal of said trigger-type flip-flop circuit and a signal obtained through said odd/even number switching terminal; a second AND-gate supplied with an output signal of said second shift register and an output signal of said first AND-gate obtained through a first inverter; a third AND-gate supplied with an output signal of said first shift register and an output of said first AND-gate; and an OR-gate supplied with a reset signal obtained through said reset signal input terminal and a second inverter and the outputs of said second and third AND-gates, for producing the load pulse.
Claim 5
Dependent Claim
44 words
A frequency-dividing circuit as claimed in claim 2 in which said preset data n is described by an equation n=(N-5/2) when the denominator N of the frequency-dividing ratio is an odd number, and described by an equation n=(N-4/2) when N is an even number.
Claim 6
Dependent Claim
149 words
A frequency-dividing circuit as claimed in claim 1 in which a denominator N (N is an integer) of the frequency-dividing ratio 1/N is an odd number, and said load pulse generation circuit comprises: a first AND-gate supplied with output signals of said second shift register and said trigger-type flip-flop circuit; a second AND-gate supplied with an output signal of said first shift register and an inverted output signal of said trigger-type flip-flop circuit; a reset signal input terminal connected to said first and second shift registers and said trigger-type flip-flop circuit, said reset signal input terminal being supplied with a reset signal when said first and second shift registers and said trigger-type flip-flop circuit are to be reset; and an OR-gate supplied with outputs of said first and second AND-gates and the reset signal obtained through said reset signal input terminal and an inverter, for producing the load pulse.
Claim 7
Dependent Claim
91 words
A frequency-dividing circuit as claimed in claim 1 in which a denominator N (N is an integer) of the frequency-dividing ratio 1/N is an even number, and said load pulse generation circuit comprises: a reset signal input terminal connected to said shifting circuit and said trigger-type flip-flop circuit, said reset signal input terminal being supplied with a reset signal when said shifting circuit and said trigger-type flip-flop circuit are to be reset, said load pulse generation circuit being further supplied with the reset signal obtained through said reset signal input terminal.
Claim 8
Dependent Claim
43 words
A frequency-dividing circuit as claimed in claim 6 in which said load pulse generation circuit has an inverting circuit for inverting said reset signal, and an OR-circuit supplied with outputs of said shifting circuit and said inverting circuit, for producing the load pulse.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-04-17 | 1987-10-17 | 1988-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-04-17 | 1991-10-17 | 1992-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-04-17 | 1995-10-17 | 1996-04-17 | $7700.00 | Window Closed / Lapsed |