US5550079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating silicide shunt of dual-gate CMOS device
Assignee: United Microelectronics Corp
•
Filing: 1995-06-15
•
Granted: 1996-08-27
•
Expires: 2015-06-15
Abstract
Abstract A method for fabricating a silicide shunt for use in dual-gate CMOS devices makes use of a nitrogen-containing silicide layer overlying the juncture between the P-type polysilicon layer and the N-type polysilicon layer. The nitrogen-containing silicide layer is formed by implanting nitrogen-containing ions, such as 28 N 2 + , into a partial or overall silicide shunt which was originally deposited over the P-type polysilicon layer and N-type polysilicon layer. Therefore, the nitrogen-containing silicide layer can serve as a diffusion barrier layer retarding the lateral dopant diffusion of these polysilicon layers via the silicide shunt.
Inventors
- 👤 Jengping Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:28
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
98 words
A method for fabricating a silicide shunt for dual-gate CMOS devices in a semiconducting substrate having a dielectric layer to isolate a first well region and a second well region therebetween, comprising: (a) forming a first conducting layer covering said first well region and a second conducting layer covering said second well region, a junction formed between the first and second conducting layers and above said dielectric layer; (b) forming a silicide layer overlying said first conducting layer and said second conducting layer; and (c) forming a nitrogen-containing silicide layer on said junction through an ion implantation procedure.
Claim 2
Independent Claim
98 words
A method for fabricating a silicide shunt for dual-gate CMOS devices in a semiconducting substrate having a dielectric layer to isolate a first well region and a second well region therebetween, comprising: (a) forming a first conducting layer covering said first well region and a second conducting layer covering said second well region, a junction formed between the first and second conducting layers and above said dielectric layer; (b) forming a silicide layer overlying said first conducting layer and said second conducting layer; and (c) forming a nitrogen-containing silicide layer on said junction through an ion implantation procedure.
Claim 3
Dependent Claim
22 words
The method as in claim 1, wherein said implantation procedure of the step (c) makes use of 28 N 2 + ions.
Claim 4
Dependent Claim
34 words
The method as in claim 2, wherein the implantation energy is in the range of 30-150 KeV and the implantation dosage is in the range of 1×10 15 to 5×10 16 atoms/cm 2 .
Claim 5
Dependent Claim
35 words
The method as in claim 1, wherein said first and second conducting layers are formed by means of a polysilicon layer doped with impurities of a first conductivity type and a second conductivity type, respectively.
Claim 6
Dependent Claim
20 words
The method as in claim 4, wherein said first conductivity type is N-type and said second conductivity type is P-type.
Claim 7
Dependent Claim
20 words
The method as in claim 5, wherein said first conductivity type is P-type and said second conductivity type is N-type.
Claim 8
Dependent Claim
13 words
The method as in claim 1, wherein said silicide layer is titanium silicide.
Claim 9
Dependent Claim
27 words
The method as claimed in claim 1 wherein said silicide layer overlying said first conducting layer and said second conducting layer is formed as a continuous layer.
Claim 10
Independent Claim
99 words
A method for fabricating a silicide shunt for dual-gate CMOS devices in a semiconducting substrate having a dielectric layer to isolate a first well region and a second well region therebetween, comprising: (a) forming a first conducting layer covering said first well region and a second conducting layer covering said second well region, a junction formed between the first and second conducting layers and above said dielectric layer; (b) forming a silicide layer overlying said first conducting layer and said second conducting layer; and (c) converting said silicide layer into a nitrogen-containing silicide layer through an ion implantation procedure.
Claim 11
Independent Claim
99 words
A method for fabricating a silicide shunt for dual-gate CMOS devices in a semiconducting substrate having a dielectric layer to isolate a first well region and a second well region therebetween, comprising: (a) forming a first conducting layer covering said first well region and a second conducting layer covering said second well region, a junction formed between the first and second conducting layers and above said dielectric layer; (b) forming a silicide layer overlying said first conducting layer and said second conducting layer; and (c) converting said silicide layer into a nitrogen-containing silicide layer through an ion implantation procedure.
Claim 12
Dependent Claim
18 words
The method as in claim 9, wherein said implantation procedure makes use of 28 N 2 + ions.
Claim 13
Dependent Claim
32 words
The method as in claim 10, wherein the implantation energy is in the range of 30-150 KeV and the implantation dosage is in the range of 1×10 15 to 5×10 16 .
Claim 14
Dependent Claim
35 words
The method as in claim 9, wherein said first and second conducting layers are formed by means of a polysilicon layer doped with impurities of a first conductivity type and a second conductivity type, respectively.
Claim 15
Dependent Claim
20 words
The method as in claim 12, wherein said first conductivity type is N-type and said second conductivity type is P-type.
Claim 16
Dependent Claim
20 words
The method as in claim 12, wherein said first conductivity type is P-type and said second conductivity type is N-type.
Claim 17
Dependent Claim
13 words
The method as in claim 9, wherein said silicide layer is titanium silicide.
Claim 18
Dependent Claim
27 words
The method as claimed in claim 9 wherein said silicide layer overlying said first conducting layer and said second conducting layer is formed as a continuous layer.
Claim 19
Independent Claim
106 words
A method for fabricating a silicide shunt for dual-gate CMOS devices in a semiconducting substrate having a dielectric layer to isolate a first well region and a second well region therebetween, comprising: (a) forming a first conducting layer covering said first well region and a second conducting layer covering said second well region, a junction formed between the first and second conducting layers and above said dielectric layer; (b) etching and patterning said first and second conducting layers forming a gate region; (c) forming a silicide layer overlying said gate region; and (d) forming a nitrogen-containing silicide layer above said junction through an ion implantation procedure.
Claim 20
Independent Claim
106 words
A method for fabricating a silicide shunt for dual-gate CMOS devices in a semiconducting substrate having a dielectric layer to isolate a first well region and a second well region therebetween, comprising: (a) forming a first conducting layer covering said first well region and a second conducting layer covering said second well region, a junction formed between the first and second conducting layers and above said dielectric layer; (b) etching and patterning said first and second conducting layers forming a gate region; (c) forming a silicide layer overlying said gate region; and (d) forming a nitrogen-containing silicide layer above said junction through an ion implantation procedure.
Claim 21
Dependent Claim
13 words
The method as in claim 18, wherein said silicide layer is titanium silicide.
Claim 22
Dependent Claim
16 words
The method as in claim 16, wherein the step (c) utilizes two-step rapid thermal annealing (RTA).
Claim 23
Dependent Claim
18 words
The method as in claim 17, wherein said implantation procedure makes use of 28 N 2 + ions.
Claim 24
Dependent Claim
32 words
The method as in claim 20, wherein the implantation energy is in the range of 30-150 KeV and the implantation dosage is in the range of 1×10 15 to 5×10 16 .
Claim 25
Dependent Claim
35 words
The method as in claim 17, wherein said first and second conducting layers are formed by means of a polysilicon layer doped with impurities of a first conductivity type and a second conductivity type, respectively.
Claim 26
Dependent Claim
20 words
The method as in claim 22, wherein said first conductivity type is N-type and said second conductivity type is P-type.
Claim 27
Dependent Claim
20 words
The method as in claim 22, wherein said first conductivity type is P-type and said second conductivity type is N-type.
Claim 28
Dependent Claim
27 words
The method as claimed in claim 15 wherein said silicide layer overlying said first conducting layer and said second conducting layer is formed as a continuous layer.
References Cited (Backward Citations)
US4703552A
Cited
EP0337481A2
Cited
US5103272A
Cited
US5190893A
Cited
US5355010A
Cited
US5389575A
Cited
US5369304A
Cited
US5468669A
Cited
US5508212A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |