Phase-locked loop and resulting frequency multiplier

Claim 2

A phase-locked loop circuit, comprising: a phase comparator for comparing an input signal with a negative feedback signal to produce at least one comparator output signal; a delay circuit having first and second inputs and at least one output, for producing at said at least one output the negative feedback signal, said first input connected to receive said input signal, said second input connected to receive a digital command signal; a digital phase command device connected to the phase comparator and to the delay circuit for producing the digital command signal responsive to said at least one comparator output signal and for providing the command signal to said second input of said delay circuit; and wherein said delay circuit introduces a controllable phase delay between the input signal applied to its first input and the negative feedback signal produced at its at least one output, causing said negative feedback signal to correspond in phase and frequency to said input signal.

Claim 3

The circuit as defined by claim 1, wherein the delay circuit is composed of an integral number (N) of delay elements connected in series, each delay element producing equal respective delays at said at least one output and the total delay of the delay circuit encompasses the time interval between two recurring predetermined edges of the input signal.

Claim 4

A phase-locked loop circuit, comprising: a phase comparator for comparing an input signal with a negative feedback signal to produce at least one comparator output signal; a delay circuit having first and second inputs and at least one output, for producing at said at least one output the negative feedback signal, said first input connected to receive said input signal, said second input connected to receive a command signal; a digital phase command device connected to the phase comparator and to the delay circuit for producing the command signal responsive to said at least one comparator output signal and for providing the command signal to said second input of said delay circuit; wherein said delay circuit introduces a controllable phase delay between the input signal applied to its first input and the negative feedback signal produced at its at least one output, causing said negative feedback signal to correspond in phase and frequency to said input signal; and wherein the phase comparator includes at least one pair of flip-flops sensitive to a predetermined recurring edge of the input signal, said flip flops including clock inputs and data inputs, means connecting the data inputs to respectively receive the input signal and the negative feedback signal, and means connecting the clock inputs to respectively receive the negative feedback signal and the input signal.

Claim 5

A phase-locked loop circuit, comprising: a phase comparator for comparing an input signal with a negative feedback signal to produce at least one comparator output signal; a delay circuit having first and second inputs and at least one output, for producing at said at least one output the negative feedback signal, said first input connected to receive said input signal, said second input connected to receive a command signal; a digital phase command device connected to the phase comparator and to the delay circuit for producing the command signal responsive to said at least one comparator output signal and for providing the command signal to said second input of said delay circuit; wherein said delay circuit introduces a controllable phase delay between the input signal applied to its first input and the negative feedback signal produced at its at least one output, causing said negative feedback signal to correspond in phase and frequency to said input signal; and wherein the phase comparator includes at least one pair of flip-flops sensitive to a predetermined recurring edge of the input signal, said flip flops including clock inputs and data inputs, means connecting the data inputs to respectively receive the input signal and the negative feedback signal, and means connecting the clock inputs to respectively receive the negative feedback signal and the input signal.

Claim 6

A frequency multiplier, comprising: a phase comparator for comparing an input signal with a negative feedback signal to produce at least one comparatory output signal; a delay circuit having first and second inputs, a plurality of outputs for producing variable phase delayed signals exhibiting equal delays therebetween and means for producing the negative feedback signal from a last delayed output signal, said first input connected to receive said input signal, said second input connected to receive a digital command signal, said plurality of outputs connected to a logical adder; a digital phase command device connected to the phase comparator and to the delay circuit for producing the digital command signal responsive to said at least one comparator output signal and for providing the digital command signal to said second input of said delay circuit; and said logical adder comprising a tree circuit of EXCLUSIVE OR gates connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal.

Claim 7

A frequency multiplier, comprising: a phase comparator for comparing an input signal with a negative feedback signal to produce at least one comparatory output signal; a delay circuit having first and second inputs, a plurality of outputs for producing variable phase delayed signals exhibiting equal delays therebetween and means for producing the negative feedback signal from a last delayed output signal, said first input connected to receive said input signal, said second input connected to receive a digital command signal, said plurality of outputs connected to a logical adder; a digital phase command device connected to the phase comparator and to the delay circuit for producing the digital command signal responsive to said at least one comparator output signal and for providing the digital command signal to said second input of said delay circuit; and said logical adder comprising a tree circuit of EXCLUSIVE OR gates connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal.

Claim 8

A frequency multiplier, comprising: a phase comparator for comparing an input signal with a negative feedback signal to produce at least one comparatory output signal; a delay circuit having first and second inputs, a plurality of outputs for producing variable phase delayed signals exhibiting equal delays therebetween and means for producing the negative feedback signal from a last delayed output signal, said first input connected to receive said input signal, said second input connected to receive a command signal, said plurality of outputs connected to a logical adder; a digital phase command device connected to the phase comparator and to the delay circuit for producing the command signal responsive to said at least one comparator output signal and for providing the command signal to said second input of said delay circuit; said logical adder comprising a tree circuit of EXCLUSIVE OR gates connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; and wherein the delay circuit includes an integral number (N) of delay elements connected in series and producing equal respective delays sharing the time interval between two recurring predetermined edges of the input signal, said plurality of variable phase delayed signals provided from the respective delay elements, and means for sampling the negative feedback signal from the output of the last delay element.

Claim 9

A frequency multiplier, comprising: a phase comparator for comparing an input signal with a negative feedback signal to produce at least one comparatory output signal; a delay circuit having first and second inputs, a plurality of outputs for producing variable phase delayed signals exhibiting equal delays therebetween and means for producing the negative feedback signal from a last delayed output signal, said first input connected to receive said input signal, said second input connected to receive a command signal, said plurality of outputs connected to a logical adder; a digital phase command device connected to the phase comparator and to the delay circuit for producing the command signal responsive to said at least one comparator output signal and for providing the command signal to said second input of said delay circuit; said logical adder comprising a tree circuit of EXCLUSIVE OR gates connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; and wherein the delay circuit includes an integral number (N) of delay elements connected in series and producing equal respective delays sharing the time interval between two recurring predetermined edges of the input signal, said plurality of variable phase delayed signals provided from the respective delay elements, and means for sampling the negative feedback signal from the output of the last delay element.

Claim 10

A frequency multiplier, comprising: a phase comparator for comparing an input signal with a negative feedback signal to produce at least one comparatory output signal; a delay circuit having first and second inputs, a plurality of outputs for producing variable phase delayed signals exhibiting equal delays therebetween and means for producing the negative feedback signal from a last delayed output signal, said first input connected to receive said input signal, said second input connected to receive a command signal, said plurality of outputs connected to a logical adder; a digital phase command device connected to the phase comparator and to the delay circuit for producing the command signal responsive to said at least one comparator output signal and for providing the command signal to said second input of said delay circuit; said logical adder comprising a tree circuit of EXCLUSIVE OR gates connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; and wherein the delay circuit is composed of an integral number (N) of delay elements connected in series, the delayed input signal comprises delayed output signals from the respective delay elements, and further including selection device means for connecting the negative feedback signal from one of the delay elements and disconnecting from the delay element in which the negative feedback signal is connected the following series connected delay elements.

Claim 11

A frequency multiplier, comprising: a phase comparator for comparing an input signal with a negative feedback signal to produce at least one comparatory output signal; a delay circuit having first and second inputs, a plurality of outputs for producing variable phase delayed signals exhibiting equal delays therebetween and means for producing the negative feedback signal from a last delayed output signal, said first input connected to receive said input signal, said second input connected to receive a command signal, said plurality of outputs connected to a logical adder; a digital phase command device connected to the phase comparator and to the delay circuit for producing the command signal responsive to said at least one comparator output signal and for providing the command signal to said second input of said delay circuit; said logical adder comprising a tree circuit of EXCLUSIVE OR gates connected to receive the variable phase delayed signals and to provide an output signal from the multiplier which is an integral multiple of said input signal; and wherein the delay circuit is composed of an integral number (N) of delay elements connected in series, the delayed input signal comprises delayed output signals from the respective delay elements, and further including selection device means for connecting the negative feedback signal from one of the delay elements and disconnecting from the delay element in which the negative feedback signal is connected the following series connected delay elements.

Claim 12

A frequency multiplier comprising: a phase comparator which receives an input signal of a period (T) and a negative feedback signal and generates an output signal; a variable-delay circuit receiving the input signal and generating delayed output signals successively and equally delayed from the input signal; means for producing the negative feedback signal from the last delayed output signal; a digital controller for producing a digital command signal for controlling the variable-delay circuit in response to the output signal of the phase comparator; and a tree circuit of EXCLUSIVE OR gates, which receives the delayed output signals and assigns equal propagation times between the delayed output signals applied to the tree circuit and the output of the tree circuit.

Claim 13

A frequency multiplier comprising: a phase comparator which receives an input signal of a period (T) and a negative feedback signal and generates an output signal; a variable-delay circuit receiving the input signal and generating delayed output signals successively and equally delayed from the input signal; means for producing the negative feedback signal from the last delayed output signal; a digital controller for producing a digital command signal for controlling the variable-delay circuit in response to the output signal of the phase comparator; and a tree circuit of EXCLUSIVE OR gates, which receives the delayed output signals and assigns equal propagation times between the delayed output signals applied to the tree circuit and the output of the tree circuit.

Claim 14

The multiplier as defined by claim 7, wherein the input signal is a square signal having adjacent leading and trailing edges and the variable-delay circuit comprises an integral number N of delay elements each producing a delay of T/2N.

Claim 15

The multiplier as defined in claim 7, wherein the digit means (12) for controlling the variable-delay means comprises a digital command device.

Claim 16

The multiplier as defined in claim 7, wherein the digital controller comprises a digital command device.

Claim 17

The multiplier as defined in claim 7, wherein said variable delay circuit comprises a plurality of delay elements and said means for producing the negative feedback signal comprises means for selecting said last delayed output signal from the last delayed output signal from a selected number of said plurality of delay elements, said selecting means connecting in series said selected number of delay elements and disconnecting them from the remaining delay elements.