Device for the automatic synchronisation of a local clock with a data signal, and sampling circuit for its application

Abstract

Abstract From the input data stream (D) a number of data signals (D1-D3) with increasing time delays are sepd. by delay lines 10,12,14) within an overall delay equal to the nominal clock period. The initial and delayed data are stored in memory flip-flops (B0, B1-B3) at the clock rhythm. Outputs from these memories are applied to a transition detector (9) comprising Exclusive-OR gates (16,18,20) which operate on successive pairs of data samples. One of the signals is selected as a valid sample of data phased w.r.t. the clock, and the selection is modified in accordance with the predetermined criterion.

Inventors

• 👤 Michel Servel
• 👤 Alain Thomas

Bibliographic Details