Patent EP0168330A1 successfully refreshed from Google Patents.
EP0168330A1
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EP
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Device for the automatic synchronisation of a local clock with a data signal, and sampling circuit for its application
Assignee: SERVEL, MICHEL
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Filing: 1985-07-15
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Granted: —
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Expires: 2005-07-15
Abstract
Abstract From the input data stream (D) a number of data signals (D1-D3) with increasing time delays are sepd. by delay lines 10,12,14) within an overall delay equal to the nominal clock period. The initial and delayed data are stored in memory flip-flops (B0, B1-B3) at the clock rhythm. Outputs from these memories are applied to a transition detector (9) comprising Exclusive-OR gates (16,18,20) which operate on successive pairs of data samples. One of the signals is selected as a valid sample of data phased w.r.t. the clock, and the selection is modified in accordance with the predetermined criterion.
Inventors
- 👤 Michel Servel
- 👤 Alain Thomas
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 06:11
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338
Claims Analysis
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References Cited (Backward Citations)
US3908084A
Cited
WO1981001226A1
Cited
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