Patent US5546018A successfully refreshed from Google Patents.
US5546018A
Expired / Lapsed
US
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Fast carry structure with synchronous input
Assignee: Xilinx Inc
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Filing: 1995-08-09
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Granted: 1996-08-13
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Expires: 2015-08-09
Abstract
Abstract Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions. In some embodiments, the circuit also includes structures which allow efficient implementation of a loadable counter and related applications.
Inventors
- 👤 Bernard I. New
- 👤 Steven P. Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:49
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503; G06F7/505; G06F7/506; G06F7/507; H03K19/177; H03K19/17724; H03K19/17728; H03K19/17736; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4812
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
143 words
A programmable logic device comprising a sequence of logic blocks, each logic block having at least one circuit comprising: an input terminal for providing an input signal (A i or Al i ); a ripple-in terminal (C i ) and a ripple-out terminal (C i+1 ); a ripple-chain multiplexer (923) for connecting one of said input terminal and said ripple-in terminal to said ripple-out terminal; a function generator (903) for generating a function generator output signal which is a function of said first input signal and at least one other input signal; a flip flop (929) providing a Q output signal; means (928 or wire) for providing said function to said flip flop; and means (814 or wire) for providing a control signal (P i ) for controlling said ripple-chain multiplexer, said control signal being selected from at least said Q output signal.
Claim 2
Dependent Claim
143 words
A programmable logic device comprising a sequence of logic blocks, each logic block having at least one circuit comprising: an input terminal for providing an input signal (A i or Al i ); a ripple-in terminal (C i ) and a ripple-out terminal (C i+1 ); a ripple-chain multiplexer (923) for connecting one of said input terminal and said ripple-in terminal to said ripple-out terminal; a function generator (903) for generating a function generator output signal which is a function of said first input signal and at least one other input signal; a flip flop (929) providing a Q output signal; means (928 or wire) for providing said function to said flip flop; and means (814 or wire) for providing a control signal (P i ) for controlling said ripple-chain multiplexer, said control signal being selected from at least said Q output signal.
Claim 3
Dependent Claim
46 words
A programmable logic device as in claim 1 in which said means for providing a control signal (P i ) for controlling said ripple-chain multiplexer is a control multiplexer, said control multiplexer receiving input signals from at least said Q output signal and said function generator.
Claim 4
Dependent Claim
162 words
A programmable logic device as in claim 1 in which said means (928) for providing said function to said flip flop comprises at least one multiplexer (928) which receives on one of its input terminals said function of said first input signal and at least one other input signal; and further comprising: an XOR gate (926) connected to receive said control multiplexer output signal (P i ) and a signal on said ripple-in terminal (C i ) which generates a sum output signal (S i ), said at least one multiplexer (928) which receives on one of its input terminals said function of said first input signal and at least one other input signal also receives on another input terminal said control multiplexer output signal (P i ); and an input multiplexer (924) which provides to said function generator said at least one other input signal, said input multiplexer being connected to alternatively provide to said function generator said sum output signal.
References Cited (Backward Citations)
US4124899B1
Cited
US4124899A
Cited
US4870302A
Cited
US4706216A
Cited
US4758745A
Cited
US5451887A
Cited
US4758745B1
Cited
US5287472A
Cited
US5343406A
Cited
EP0456475A2
Cited
US5267187A
Cited
US5198705A
Cited
US5280202A
Cited
US5396127A
Cited
US5260611A
Cited
US5258668A
Cited
US5414377A
Cited
EP0607657A1
Cited
US5317210A
Cited
US5332929A
Cited
US5352940A
Cited
US5349250A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-13 | 2000-02-12 | 2000-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-13 | 2004-02-12 | 2004-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-13 | 2008-02-12 | 2008-08-13 | $7700.00 | Window Closed / Lapsed |