Abstract A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.
A method of controlling transfer of signals from a first self-resetting logic circuit to a second self-resetting logic circuit requiring a pulsed input, the method comprising the steps of: transferring an output signal from the first logic circuit to a latch and registering the output signal in the latch under control of a clock pulse having a leading edge and a trailing edge and generating a latch output signal; resetting the first logic circuit a predetermined period of time after the clock pulse leading edge; in response to the trailing edge of the clock pulse, generating a latch output control pulse; and transferring the latch output signal to the second logic circuit on a pulsed basis in response to the latch output control pulse.
Claim 2
Independent Claim
124 words
A method of controlling transfer of signals from a first self-resetting logic circuit to a second self-resetting logic circuit requiring a pulsed input, the method comprising the steps of: transferring an output signal from the first logic circuit to a latch and registering the output signal in the latch under control of a clock pulse having a leading edge and a trailing edge and generating a latch output signal; resetting the first logic circuit a predetermined period of time after the clock pulse leading edge; in response to the trailing edge of the clock pulse, generating a latch output control pulse; and transferring the latch output signal to the second logic circuit on a pulsed basis in response to the latch output control pulse.
Claim 3
Dependent Claim
71 words
The method in accordance with claim 1 wherein the step of generating the latch output control pulse comprises generating a latch output pulse having a leading edge delayed from the trailing edge of the clock pulse by a first predetermined period of time and a trailing edge delayed from the trailing edge of the clock pulse by a second predetermined period of time longer than the first predetermined period of time.