US5329176A
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Self-timed clocking system and method for self-timed dynamic logic circuits
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-09-29
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Granted: 1994-07-12
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Expires: 2013-09-29
Abstract
Abstract A clocking system and method are provided for logic blocks having cascaded self-timed dynamic logic gates. The dynamic logic gates are precharged in parallel and collectively perform self-timed logic evaluation on vector inputs to derive a vector output. An evaluation done detector monitors the output of the logic block and determines when the vector output is valid. An edge detector detects the rising and falling edges of an arbitrary periodic timing signal. Finally, a logic block clock generator is set by the edge detector and reset by the evaluation done detector so as to provide precharging signals to the logic block, thereby defining respective precharge periods, and to provide evaluation periods for the self-timed logic evaluations in the logic block. In a specific implementation, the speed of logic evaluations is twice the speed of the system clock.
Inventors
- 👤 Robert H. Miller, Jr.
- 👤 Jeffry D. Yetter
- 👤 Glenn T. Colon-Bonet
- 👤 Robert J. Martin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:10
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/5016; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0966; H03K19/20; H03K19/21; H03K19/215
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
150 words
A system for enhancing the speed of logic evaluations through a series of cascaded self-timed dynamic logic gates, the system comprising: a logic block having cascaded dynamic logic gates which are precharged in parallel and which can collectively perform self-timed logic evaluations on vector inputs to derive a vector output; an evaluation done detector monitoring the output of said logic block and configured to determine when said vector output is valid; a logic block clock generator for outputting a clock signal which is set to a first logic level by a triggering signal and reset to a second logic level by said evaluation done detector, said logic block clock generator adapted to provide said clock signal to said logic block, said clock signal first logic level defining respective precharge periods, and said clock signal second logic level defining respective evaluation periods for said self-timed logic evaluations in said logic block.
Claim 2
Independent Claim
150 words
A system for enhancing the speed of logic evaluations through a series of cascaded self-timed dynamic logic gates, the system comprising: a logic block having cascaded dynamic logic gates which are precharged in parallel and which can collectively perform self-timed logic evaluations on vector inputs to derive a vector output; an evaluation done detector monitoring the output of said logic block and configured to determine when said vector output is valid; a logic block clock generator for outputting a clock signal which is set to a first logic level by a triggering signal and reset to a second logic level by said evaluation done detector, said logic block clock generator adapted to provide said clock signal to said logic block, said clock signal first logic level defining respective precharge periods, and said clock signal second logic level defining respective evaluation periods for said self-timed logic evaluations in said logic block.
Claim 3
Dependent Claim
27 words
The system of claim 1, further comprising an edge detector for generating said triggering signal by detecting the rising and falling edges of a periodic timing signal.
Claim 4
Dependent Claim
22 words
The system of claim 1, wherein said triggering signal comprises a waveform having an edge indicating the termination of said precharging periods.
Claim 5
Dependent Claim
39 words
The system of claim 1, further comprising a precharge done detector for providing said triggering signal, said precharge done detector configured to monitor the output of said logic block and configured to determine when said vector output is invalid.
Claim 6
Dependent Claim
53 words
The system of claim 1, further comprising a plurality of vector outputs and wherein said evaluation done detector comprises an OR logic gate for each of said vector outputs and an AND logic gate for collectively evaluating the OR logic gate outputs so as to determine when all said vector outputs are valid.
Claim 7
Dependent Claim
13 words
The system of claim 1 implemented in a mathematical circuit directed to division.
Claim 8
Dependent Claim
16 words
The system of claim 2, wherein said periodic timing signal is synchronous with a system clock.
Claim 9
Dependent Claim
16 words
The system of claim 2, wherein said periodic timing signal is asynchronous to a system clock.
Claim 10
Independent Claim
127 words
A method for utilizing a self-timed dynamic logic block having precharge and evaluation periods at a rate which is faster than a system clock while maintaining synchronous operation with the system clock, comprising the steps of: (1) providing a triggering signal which is synchronous to the system clock; and (2) performing the following steps during a period of the system clock; (a) performing a first self-timed logic evaluation on a first vector input at the rising edge of said triggering signal; (b) generating a first precharge upon detecting the vector output as valid; (c) performing a second self-timed logic evaluation on a second vector input at the falling edge of said triggering signal; and (d) generating a second precharge upon detecting the second vector output as valid.
Claim 11
Independent Claim
127 words
A method for utilizing a self-timed dynamic logic block having precharge and evaluation periods at a rate which is faster than a system clock while maintaining synchronous operation with the system clock, comprising the steps of: (1) providing a triggering signal which is synchronous to the system clock; and (2) performing the following steps during a period of the system clock; (a) performing a first self-timed logic evaluation on a first vector input at the rising edge of said triggering signal; (b) generating a first precharge upon detecting the vector output as valid; (c) performing a second self-timed logic evaluation on a second vector input at the falling edge of said triggering signal; and (d) generating a second precharge upon detecting the second vector output as valid.
Claim 12
Dependent Claim
15 words
The method of claim 9, wherein said triggering signal is synchronous with a system clock.
Claim 13
Dependent Claim
15 words
The method of claim 9, wherein said triggering signal is asynchronous to a system clock.
Claim 14
Dependent Claim
23 words
The method of claim 9, wherein said triggering signal is generated by the detection of the completion of said first and second precharges.
Claim 15
Independent Claim
180 words
A system for enhancing the speed of logic evaluations through a self-timed dynamic logic block having precharge and evaluation periods, the system comprising: a logic block having inputs and an output, said logic block having cascaded dynamic logic gates which are precharged during the precharge period and which performs a self-timed logic evaluation on said inputs to derive said output during the evaluation period; an evaluation done detector connected to said output, said evaluation done detector for determining when said logic block has completed said logic evaluation by sensing said output and for causing termination of said evaluation period; and means connected to said logic block and to said evaluation done detector, said means for receiving a periodic timing signal, said means for terminating said evaluation period and for commencing said precharge period by applying a precharge to said logic block after said logic block has completed said logic evaluation, said means for terminating said precharge period by terminating application of said precharge and for commencing said evaluation period at each change of logic state of said periodic timing signal.
Claim 16
Independent Claim
180 words
A system for enhancing the speed of logic evaluations through a self-timed dynamic logic block having precharge and evaluation periods, the system comprising: a logic block having inputs and an output, said logic block having cascaded dynamic logic gates which are precharged during the precharge period and which performs a self-timed logic evaluation on said inputs to derive said output during the evaluation period; an evaluation done detector connected to said output, said evaluation done detector for determining when said logic block has completed said logic evaluation by sensing said output and for causing termination of said evaluation period; and means connected to said logic block and to said evaluation done detector, said means for receiving a periodic timing signal, said means for terminating said evaluation period and for commencing said precharge period by applying a precharge to said logic block after said logic block has completed said logic evaluation, said means for terminating said precharge period by terminating application of said precharge and for commencing said evaluation period at each change of logic state of said periodic timing signal.
Claim 17
Dependent Claim
51 words
The system of claim 13, wherein said periodic timing signal, said inputs, and said output are synchronous to a system clock and wherein said periodic timing signal exhibits a higher frequency than said system clock so that said system performs said logic evaluation faster than a period of said system block.
Claim 18
Dependent Claim
97 words
The system of claim 13, wherein said means comprises: an edge detector for receiving said periodic timing signal, for detecting rising and falling edges of said periodic timing signal, and for generating a triggering signal; and a logic block clock generator connected to said edge detector, to said logic block, and to said done detector, said logic block clock generator for receiving said triggering signal, for applying said precharge to said logic block after said logic block has completed said logic evaluation, and for terminating said precharge at each of said edges of said periodic timing signal.
Claim 19
Dependent Claim
55 words
The system of claim 13, wherein said logic block comprises a plurality of vector outputs and wherein said evaluation done detector comprises an OR logic gate for each of said vector outputs and an AND logic gate for collectively evaluating the OR logic gate outputs so as to determine when said evaluation period is complete.
Claim 20
Dependent Claim
39 words
The system of claim 13, further comprising a precharge done detector connected to said output, said precharge done detector for determining when said logic block have completed precharging by sensing said output and for generating said periodic timing signal.
Claim 21
Dependent Claim
28 words
The system of claim 15, wherein said logic block clock generator is a flip-flop, said triggering signal for setting said flip-flop, said done detector for resetting said flip-flop.
Claim 22
Dependent Claim
19 words
The system of claim 16, wherein each of said vector outputs is defined by greater than two logic paths.
Claim 23
Independent Claim
192 words
A system for utilizing a self-timed dynamic logic block having precharge and evaluation periods at a rate which is twice as fast as a system clock while maintaining synchronous operation with the system clock, the system comprising: a logic block having inputs and an output, said logic block having cascaded dynamic logic gates which are precharged during the precharge period and which performs a self-timed logic evaluation on said inputs to derive said output during the evaluation period; an evaluation done detector connected to said output, said evaluation done detector for determining when said logic block has completed said logic evaluation by sensing said output and for causing termination of said evaluation period; and means connected to said logic block and to said evaluation done detector, said means for receiving the system block, said means for terminating said evaluation period and for connecting said precharge period by applying a precharge to said logic block after said logic block has completed said logic evaluation, said means for terminating said precharge period by terminating application of said precharge and for commencing said evaluation period at each change of logic state of said system clock.
Claim 24
Independent Claim
192 words
A system for utilizing a self-timed dynamic logic block having precharge and evaluation periods at a rate which is twice as fast as a system clock while maintaining synchronous operation with the system clock, the system comprising: a logic block having inputs and an output, said logic block having cascaded dynamic logic gates which are precharged during the precharge period and which performs a self-timed logic evaluation on said inputs to derive said output during the evaluation period; an evaluation done detector connected to said output, said evaluation done detector for determining when said logic block has completed said logic evaluation by sensing said output and for causing termination of said evaluation period; and means connected to said logic block and to said evaluation done detector, said means for receiving the system block, said means for terminating said evaluation period and for connecting said precharge period by applying a precharge to said logic block after said logic block has completed said logic evaluation, said means for terminating said precharge period by terminating application of said precharge and for commencing said evaluation period at each change of logic state of said system clock.
Claim 25
Dependent Claim
94 words
The system of claim 20, wherein said means comprises: an edge detector for receiving said system clock, for detecting rising and falling edges of said system clock, and for generating a triggering signal; and a logic block clock generator connected to said edge detector, to said logic block, and to said done detector, said logic block clock generator for receiving said triggering signal, for applying said precharge to said logic block after said logic block has completed said logic evaluation, and for terminating said precharge at each of said edges of said system clock.
Claim 26
Dependent Claim
55 words
The system of claim 20, wherein said logic block comprises a plurality of vector outputs and wherein said evaluation done detector comprises an OR logic gate for each of said vector outputs and an AND logic gate for collectively evaluating the OR logic gate outputs so as to determine when said evaluation period is complete.
Claim 27
Dependent Claim
38 words
The system of claim 20, further comprising a precharge done detector connected to said output, said precharge done detector for determining when said logic block have completed precharging by sensing said output and for generating said system clock.
Claim 28
Dependent Claim
28 words
The system of claim 20, wherein said logic block clock generator is a flip-flop, said triggering signal for setting said flip-flop, said done detector for resetting said flip-flop.
Claim 29
Dependent Claim
19 words
The system of claim 22, wherein each of said vector outputs is defined by greater than two logic paths.
Claim 30
Independent Claim
105 words
A method for enhancing the speed of logic evaluations through a self-timed dynamic logic block having inputs and an output and having precharge and evaluation periods, the method comprising the steps of: receiving a periodic timing signal; terminating said precharge period and commencing said evaluation period at each change of logic state of said periodic timing signal; performing a self-timed logic evaluation on the inputs to derive the output during said evaluation period; detecting when said evaluation is complete by monitoring the output; and terminating said evaluation period and connecting application of a precharge to the logic block after detecting completion of said logic evaluation.
Claim 31
Independent Claim
105 words
A method for enhancing the speed of logic evaluations through a self-timed dynamic logic block having inputs and an output and having precharge and evaluation periods, the method comprising the steps of: receiving a periodic timing signal; terminating said precharge period and commencing said evaluation period at each change of logic state of said periodic timing signal; performing a self-timed logic evaluation on the inputs to derive the output during said evaluation period; detecting when said evaluation is complete by monitoring the output; and terminating said evaluation period and connecting application of a precharge to the logic block after detecting completion of said logic evaluation.
Claim 32
Dependent Claim
25 words
The method of claim 26, further comprising the step of performing logic evaluations with said logic block at twice the speed of the system clock.
Claim 33
Independent Claim
110 words
A method for utilizing self-timed dynamic logic block having precharge and evaluation periods at a rate which is twice the speed of a system clock while maintaining synchronous operation with the system clock, the method comprising the steps of: receiving the system clock; terminating said precharge period and commencing said evaluation period at each change of logic state of said system clock; performing a self-timed logic evaluation on the inputs to derive the output during said evaluation period; detecting when said evaluation is complete by monitoring the output; and terminating said evaluation period and commencing application of a precharge to the logic block after detecting completion of said logic evaluation.
Claim 34
Independent Claim
110 words
A method for utilizing self-timed dynamic logic block having precharge and evaluation periods at a rate which is twice the speed of a system clock while maintaining synchronous operation with the system clock, the method comprising the steps of: receiving the system clock; terminating said precharge period and commencing said evaluation period at each change of logic state of said system clock; performing a self-timed logic evaluation on the inputs to derive the output during said evaluation period; detecting when said evaluation is complete by monitoring the output; and terminating said evaluation period and commencing application of a precharge to the logic block after detecting completion of said logic evaluation.
Claim 35
Dependent Claim
25 words
The method of claim 28, further comprising the step of performing logic evaluations with said logic block at twice the speed of the system clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |