US5543348A
Expired / Lapsed
US
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Controlled recrystallization of buried strap in a semiconductor memory device
Assignee: Infineon Technologies AG
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Filing: 1995-03-29
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Granted: 1996-08-06
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Expires: 2015-03-29
Abstract
Abstract A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate and an impurity-doped first conductive region is then formed by filling the trench with an impurity-doped first conductive material. The impurity-doped first conductive region is etched back to a first level within the trench. An insulating layer is then formed on a sidewall of the portion of the trench opened by the etching back of the impurity-doped first conductive region and a second conductive region is formed by filling the remainder of the trench with a second conductive material. The insulating layer and the second conductive region are etched back to a second level within the trench and an amorphous silicon layer is formed in the portion of the trench opened by the etching back of the insulating layer and the second conductive region. The undoped amorphous silicon layer is etched back to a third a level within the trench. The undoped amorphous silicon layer is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap for electrically connecting the first and second conductive layers in the trench to the source/drain region.
Inventors
- 👤 Erwin Hammerl
- 👤 Jack A. Mandelman
- 👤 Herbert L. Ho
- 👤 Junichi Shiozawa
- 👤 Reinhard J. Stengl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:21
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
222 words
A method of forming a coupled capacitor and transistor, the method comprising the steps of: forming a trench in a semiconductor substrate; forming an impurity-doped first conductive region by filling said trench with an impurity-doped first conductive material; etching back said impurity-doped first conductive region to a first level within said trench; forming an insulating layer on a sidewall of the portion of said trench opened by the etching back of said impurity-doped first conductive region; forming a second conductive region by filling the remainder of said trench with a second conductive material; etching back said insulating layer and said second conductive region to a second level within said trench; forming an undoped amorphous silicon layer in the portion of said trench opened by the etching back of said insulating layer and said second conductive region; etching back said undoped amorphous silicon layer to a third level within said trench; recrystallizing said amorphous silicon layer; outdiffusing impurities from said impurity-doped first conductive region to said semiconductor substrate through said recrystallized silicon layer; and forming a source/drain region of said transistor adjacent to an intersection of said trench and the surface of said semiconductor substrate, said outdiffused impurities and said recrystallized silicon layer constituting a buried strap for electrically connecting said first and second conductive layers in said trench to said source/drain region.
Claim 2
Independent Claim
222 words
A method of forming a coupled capacitor and transistor, the method comprising the steps of: forming a trench in a semiconductor substrate; forming an impurity-doped first conductive region by filling said trench with an impurity-doped first conductive material; etching back said impurity-doped first conductive region to a first level within said trench; forming an insulating layer on a sidewall of the portion of said trench opened by the etching back of said impurity-doped first conductive region; forming a second conductive region by filling the remainder of said trench with a second conductive material; etching back said insulating layer and said second conductive region to a second level within said trench; forming an undoped amorphous silicon layer in the portion of said trench opened by the etching back of said insulating layer and said second conductive region; etching back said undoped amorphous silicon layer to a third level within said trench; recrystallizing said amorphous silicon layer; outdiffusing impurities from said impurity-doped first conductive region to said semiconductor substrate through said recrystallized silicon layer; and forming a source/drain region of said transistor adjacent to an intersection of said trench and the surface of said semiconductor substrate, said outdiffused impurities and said recrystallized silicon layer constituting a buried strap for electrically connecting said first and second conductive layers in said trench to said source/drain region.
Claim 3
Dependent Claim
26 words
The method according to claim 1, wherein said amorphous silicon layer is recrystallized by a heat treatment at approximately 550 degrees Celsius in a nitrogen ambient.
Claim 4
Dependent Claim
42 words
The method according to claim 1, wherein a native oxide is removed from the portion of said trench opened by the etching back of said insulating layer and said second conductive region prior to the step of forming an amorphous silicon layer.
Claim 5
Dependent Claim
15 words
The method according to claim 1, wherein said impurity-doped first conductive material is N+ polysilicon.
Claim 6
Dependent Claim
35 words
The method according to claim 1, wherein the step of forming a second conductive region comprises forming an impurity-doped second conductive region by filling the remainder of said trench with an impurity-doped second conductive material.
Claim 7
Dependent Claim
15 words
The method according to claim 5, wherein said impurity-doped second conductive material is N+ polysilicon.
Claim 8
Independent Claim
175 words
A method of forming a buried strap for coupling a capacitor and a transistor, the method comprising the steps of: forming a trench in a semiconductor substrate; forming an impurity-doped first conductive region by filling said trench with an impurity-doped first conductive material; etching back said impurity-doped first conductive region to a first level within said trench; forming an insulating layer on a sidewall of the portion of said trench opened by the etching back of said impurity-doped first conductive region; forming a second conductive region by filling the remainder of said trench with a second conductive material; etching back said insulating layer and said second conductive region to a second level within said trench; forming an amorphous silicon layer in the portion of said trench opened by the etching back of said insulating layer and said second conductive region; recrystallizing said amorphous silicon layer; and outdiffusing impurities from said impurity-doped first conductive region to semiconductor substrate through said recrystallized silicon layer, whereby said outdiffused impurities and the recrystallized silicon layer form said buried strap.
Claim 9
Independent Claim
175 words
A method of forming a buried strap for coupling a capacitor and a transistor, the method comprising the steps of: forming a trench in a semiconductor substrate; forming an impurity-doped first conductive region by filling said trench with an impurity-doped first conductive material; etching back said impurity-doped first conductive region to a first level within said trench; forming an insulating layer on a sidewall of the portion of said trench opened by the etching back of said impurity-doped first conductive region; forming a second conductive region by filling the remainder of said trench with a second conductive material; etching back said insulating layer and said second conductive region to a second level within said trench; forming an amorphous silicon layer in the portion of said trench opened by the etching back of said insulating layer and said second conductive region; recrystallizing said amorphous silicon layer; and outdiffusing impurities from said impurity-doped first conductive region to semiconductor substrate through said recrystallized silicon layer, whereby said outdiffused impurities and the recrystallized silicon layer form said buried strap.
Claim 10
Dependent Claim
26 words
The method according to claim 7, wherein said amorphous silicon layer is recrystallized by a heat treatment at approximately 550 degrees Celsius in a nitrogen ambient.
Claim 11
Dependent Claim
42 words
The method according to claim 7, wherein a native oxide is removed from the portion of said trench opened by the etching back of said insulating layer and said second conductive region prior to the step of forming an amorphous silicon layer.
Claim 12
Dependent Claim
15 words
The method according to claim 7, wherein said impurity-doped first conductive material is N+ polysilicon.
Claim 13
Dependent Claim
35 words
The method according to claim 7, wherein the step of forming a second conductive region comprises forming an impurity-doped second conductive region by filling the remainder of said trench with an impurity-doped second conductive material.
Claim 14
Dependent Claim
15 words
The method according to claim 11, wherein said impurity-doped second conductive material is N+ polysilicon.
Claim 15
Independent Claim
169 words
A method of manufacturing a semiconductor memory device, the method comprising the steps of: forming a trench in a semiconductor substrate; forming a conductive region in said trench by filling said trench with a conductive material, at least an upper portion of said conductive region being insulatively spaced from said semiconductor substrate by an insulating layer and at least a portion of said conductive material being doped with impurities; etching back said conductive region and said insulating layer to a level in said trench; forming an amorphous undoped silicon layer in the portion of said trench opened by etching back said conductive region and said insulating layer; recrystallizing the amorphous undoped silicon layer; outdiffusing impurities from said impurity-doped polysilicon to said semiconductor substrate via said recrystallized silicon layer to form an outdiffused region; and forming a transfer gate having source/drain regions on a surface of said semiconductor substrate, said outdiffused region and the recrystallized silicon constituting a buried strap for electrically connecting said transfer gate to said conductive region.
Claim 16
Independent Claim
169 words
A method of manufacturing a semiconductor memory device, the method comprising the steps of: forming a trench in a semiconductor substrate; forming a conductive region in said trench by filling said trench with a conductive material, at least an upper portion of said conductive region being insulatively spaced from said semiconductor substrate by an insulating layer and at least a portion of said conductive material being doped with impurities; etching back said conductive region and said insulating layer to a level in said trench; forming an amorphous undoped silicon layer in the portion of said trench opened by etching back said conductive region and said insulating layer; recrystallizing the amorphous undoped silicon layer; outdiffusing impurities from said impurity-doped polysilicon to said semiconductor substrate via said recrystallized silicon layer to form an outdiffused region; and forming a transfer gate having source/drain regions on a surface of said semiconductor substrate, said outdiffused region and the recrystallized silicon constituting a buried strap for electrically connecting said transfer gate to said conductive region.
Claim 17
Dependent Claim
43 words
The method according to claim 13, further comprising the step of: removing a native oxide in the portion of said trench opened by etching back said conductive region and said insulating layer prior to the step of forming an amorphous undoped silicon layer.
Claim 18
Dependent Claim
25 words
The method according to claim 13, wherein the amorphous undoped silicon layer is recrystallized by heating at approximately 550 degrees Celsius in a nitrogen ambient.
References Cited (Backward Citations)
US4509990A
Cited
US4444620A
Cited
US4584025A
Cited
US4824793A
Cited
US4716548A
Cited
US4659392A
Cited
US4820652A
Cited
US4849371A
Cited
US5168366A
Cited
US4753895A
Cited
US4816893A
Cited
US4916524A
Cited
US4826300A
Cited
US4853342A
Cited
US4942554A
Cited
US4910709A
Cited
US4915746A
Cited
US5116768A
Cited
US5138420A
Cited
US4988637A
Cited
US5336629A
Cited
US5192703A
Cited
US5262662A
Cited
US5168073A
Cited
US5292678A
Cited
US5185294A
Cited
US5308783A
Cited
US5312768A
Cited
US5422294A
Cited
US5376566A
Cited
US5360758A
Cited
US5413950A
Cited
US5380673A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |