Three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories comprising trench capacitor and method for manufacturing same

Claim 1

A three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories, having a field effect transistor and one capacitor for the charges to be stored, the capacitor is created as a trench capacitor in the substrate, the capacitor including a first electrode formed by the substrate and a second electrode that stores the charges is formed by doped polycrystalline silicon that fills up the trench, the field effect transistor resides at the surface of the substrate and has an insulated gate electrode the capacitor separated by an insulating layer is arranged under the field effect transistor a recrystallized silicon layer is applied on the insulating layer and source/drain zones are arranged in the recrystallized silicon layer, the capacitor is connected with the source/drain zones via an electrically conductive contact and: in an upper portion of the trench, an asymmetrical extension of the trench opening is introduced into the substrate in the upper part of the trench, the asymmetrical extension being filled with polycrystalline silicon having the same doping as in the trench, the electrically conductive contact is established via this filled extension and representing a subregion of the second electrode of the capacitor that stores the charge; the insulating layer separating the transistor from the capacitor is arranged next to the asymmetrical extension of the trench opening in the trench having the same geometry as the lower portion of the trench; and the gate electrode of the transistor is arranged over the insulating layer and above the recrystallized silicon layer situated thereover, being arranged thereat such that the source zone generated in the recrystallized silicon layer overlaps the electrically conductive contact in the asymmetrical extension of the trench opening.