US5541876A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell fabricated by floating gate structure
Assignee: United Microelectronics Corp
•
Filing: 1994-06-01
•
Granted: 1996-07-30
•
Expires: 2014-06-01
Abstract
Abstract A memory cell and a process for making it are disclosed. The ROM code is not implanted in the floating gate for cells selected to be "off". This memory cell has a much lower threshold voltage than conventional cells and the implantation induced crystal damage is avoided.
Inventors
- 👤 Chen-Chin Hsue
- 👤 Ming-Tzong Yang
- 👤 Chung-Cheng Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:59
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H; H10; H10B; H10B20/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
79 words
A memory cell programmed in an "off" state, comprising: a gate oxide grown on a substrate of a first dopant type, wherein said gate oxide is confined between two bit lines buried in said substrate, said bit lines acting as a source and a drain, respectively, a floating gate disposed on said gate oxide, an insulating layer extending over said floating gate, a control gate extending over a said insulating layer, and ROM code implanted in said floating gate.
Claim 2
Dependent Claim
79 words
A memory cell programmed in an "off" state, comprising: a gate oxide grown on a substrate of a first dopant type, wherein said gate oxide is confined between two bit lines buried in said substrate, said bit lines acting as a source and a drain, respectively, a floating gate disposed on said gate oxide, an insulating layer extending over said floating gate, a control gate extending over a said insulating layer, and ROM code implanted in said floating gate.
Claim 3
Dependent Claim
96 words
A memory cell comprising: first and second parallel buried bit lines of a second dopant type formed in a substrate of a first dopant type, a channel region in said substrate separating the buried bit lines, a gate oxide layer located on the substrate over said channel, wherein said gate oxide layer is confined between said first and second parallel buried bit lines, a floating gate deposited over the gate oxide layer, an insulating layer formed over the floating gate, a control gate formed over said insulating layer, and ROM code implanted in said floating gate.
Claim 4
Dependent Claim
96 words
A memory cell comprising: first and second parallel buried bit lines of a second dopant type formed in a substrate of a first dopant type, a channel region in said substrate separating the buried bit lines, a gate oxide layer located on the substrate over said channel, wherein said gate oxide layer is confined between said first and second parallel buried bit lines, a floating gate deposited over the gate oxide layer, an insulating layer formed over the floating gate, a control gate formed over said insulating layer, and ROM code implanted in said floating gate.
Claim 5
Dependent Claim
27 words
The memory cell of claim 2, wherein said gate oxide layer has a thickness of about 150Å and said insulating layer has a thickness of about 150Å.
Claim 6
Dependent Claim
17 words
The memory cell of claim 2, wherein said insulating layer is preferably S i O 2 .
Claim 7
Dependent Claim
80 words
An array of memory cells, comprising: a substrate of a first dopant type, a plurality of parallel buried bit lines of a second dopant type formed in said substrate, a plurality of floating gates confined between said parallel buried bit lines, a plurality of polysilicon wordlines formed over said floating gates and orthogonal to said buried bit lines, an insulating layer separating said floating gates from said polysilicon wordlines, and ROM code implanted in cells selected to be programmed "off".
Claim 8
Dependent Claim
80 words
An array of memory cells, comprising: a substrate of a first dopant type, a plurality of parallel buried bit lines of a second dopant type formed in said substrate, a plurality of floating gates confined between said parallel buried bit lines, a plurality of polysilicon wordlines formed over said floating gates and orthogonal to said buried bit lines, an insulating layer separating said floating gates from said polysilicon wordlines, and ROM code implanted in cells selected to be programmed "off".
Claim 9
Dependent Claim
64 words
A process for programming a memory cell having a source, a drain, a floating gate, an insulating layer and a control gate separated from the floating gate by the insulating layer, comprising: selecting if said cell is to be programmed off or on, if said cell is selected off, implanting said floating gate with a ROM code confined between said source and said drain.
Claim 10
Dependent Claim
64 words
A process for programming a memory cell having a source, a drain, a floating gate, an insulating layer and a control gate separated from the floating gate by the insulating layer, comprising: selecting if said cell is to be programmed off or on, if said cell is selected off, implanting said floating gate with a ROM code confined between said source and said drain.
Claim 11
Dependent Claim
63 words
A ROM cell, comprising: a substrate including first and second bit lines spaced apart by a channel, a floating gate formed over said channel, wherein said floating gate is confined between the first and second bit lines, a control gate formed over said floating gate, and said floating gate being implanted with a ROM code if said cell is programmed to be off.
Claim 12
Dependent Claim
63 words
A ROM cell, comprising: a substrate including first and second bit lines spaced apart by a channel, a floating gate formed over said channel, wherein said floating gate is confined between the first and second bit lines, a control gate formed over said floating gate, and said floating gate being implanted with a ROM code if said cell is programmed to be off.
Claim 13
Dependent Claim
73 words
A ROM array, comprising: a plurality of cells formed in a substrate, each of said cells including first and second bit lines separated by a channel, a floating gate formed over said channel, axed a control gate formed over said floating gate, wherein said floating gate is confuted between said first and second bit lines, and wherein the floating gates of a first plurality of said cells are implanted with a ROM code.
Claim 14
Dependent Claim
73 words
A ROM array, comprising: a plurality of cells formed in a substrate, each of said cells including first and second bit lines separated by a channel, a floating gate formed over said channel, axed a control gate formed over said floating gate, wherein said floating gate is confuted between said first and second bit lines, and wherein the floating gates of a first plurality of said cells are implanted with a ROM code.
References Cited (Backward Citations)
US3660819A
Cited
US4114255A
Cited
US4142926B1
Cited
US4142926A
Cited
US4099196A
Cited
US4203138A
Cited
US4266283A
Cited
US4317272A
Cited
US4328565A
Cited
US4412310A
Cited
US4432075A
Cited
US4868629A
Cited
US4868619A
Cited
US4797856A
Cited
US5115288A
Cited
US5220528A
Cited
US5289026A
Cited
US5349553A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-30 | 2000-01-29 | 2000-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-30 | 2004-01-29 | 2004-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-30 | 2008-01-29 | 2008-07-30 | $7700.00 | Window Closed / Lapsed |