Patent US5537076A successfully refreshed from Google Patents.
US5537076A
Expired / Lapsed
US
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Negative resistance circuit and inverter circuit including the same
Assignee: NEC Corp
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Filing: 1994-05-02
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Granted: 1996-07-16
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Expires: 2014-05-02
Abstract
Abstract A new negative resistance circuit comprises a first N-channel enhancement FET (E-FET), an N-channel depletion FET as a load element connected to the first N-channel E-FET to form a series branch connected between negative resistance ports, and a second N-channel E-FET having source-drain path parallel to the series branch. The gate of the second N-channel E-FET is connected to the connection node between the load element and the first E-FET, while the gate electrode of the first E-FET is connected to a control port for controlling current-voltage characteristic between the negative resistance ports. The negative resistance circuit can be used in an inverter to enable the inverter to have a hysteretic function or a multivalued logic function.
Inventors
- 👤 Masahiro Fujii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:47
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
207 words
A negative resistance circuit comprising: first and second enhancement FETs each having a first electrode and a second electrode and a gate electrode controlling current flowing between said first and second electrodes, a conductivity type of said first enhancement FET being the same as a conductivity type of said second enhancement FET; a load element having first and second ends, wherein said first end is connected to said first enhancement FET and said second end is connected to a first port of said negative resistance circuit, whereby said load element and said first enhancement FET form a first branch connected between said first port and a second port of said negative resistance circuit, said first and second electrodes of said second enhancement FET being connected between said first and second ports to form a second branch parallel to said first branch, said gate electrode of said second enhancement FET being connected to said second electrode of said first enhancement FET; and means for maintaining a constant voltage between said gate electrode of said first enhancement FET and said first port, said first and second ports receiving first and second voltages, wherein a current-voltage characteristic between said first port and said second port exhibits a negative resistance function.
Claim 2
Dependent Claim
207 words
A negative resistance circuit comprising: first and second enhancement FETs each having a first electrode and a second electrode and a gate electrode controlling current flowing between said first and second electrodes, a conductivity type of said first enhancement FET being the same as a conductivity type of said second enhancement FET; a load element having first and second ends, wherein said first end is connected to said first enhancement FET and said second end is connected to a first port of said negative resistance circuit, whereby said load element and said first enhancement FET form a first branch connected between said first port and a second port of said negative resistance circuit, said first and second electrodes of said second enhancement FET being connected between said first and second ports to form a second branch parallel to said first branch, said gate electrode of said second enhancement FET being connected to said second electrode of said first enhancement FET; and means for maintaining a constant voltage between said gate electrode of said first enhancement FET and said first port, said first and second ports receiving first and second voltages, wherein a current-voltage characteristic between said first port and said second port exhibits a negative resistance function.
Claim 3
Dependent Claim
42 words
A negative resistance circuit as defined in claim 1 wherein said gate electrode of said first enhancement FET is connected to a control port of said negative resistance circuit for controlling said current-voltage characteristic between said first port and said second port.
Claim 4
Dependent Claim
23 words
A negative resistance circuit as defined in claim 1 wherein each of said first and second enhancement FETs comprises an N-channel enhancement FET.
Claim 5
Dependent Claim
16 words
A negative resistance circuit as defined in claim 1, wherein said load element comprises a FET.
Claim 6
Dependent Claim
19 words
A negative resistance circuit as defined in claim 4 wherein said load element comprises a depletion mode load element.
Claim 7
Dependent Claim
291 words
An inverter circuit, comprising: a negative resistance circuit including: first and second enhancement FETs each having a first electrode and a second electrode and a gate electrode controlling current flowing between said first and second electrodes, a conductivity type of said first enhancement FET being the same as a conductivity type of said second enhancement FET; a load element having first and second ends wherein said first end is connected to said first enhancement FET and said second end is connected to a first port of said negative resistance circuit, whereby said load element and said first enhancement FET form a first branch connected between said first port and a second port of said negative resistance circuit, said first and second electrodes of said second enhancement FET being connected between said first and second ports to form a second branch parallel to said first branch, said gate electrode of said second enhancement FET being connected to said second electrode of said first enhancement FET; and means for maintaining a constant voltage between said gate electrode of said first enhancement FELT and said first port, and wherein said inverter circuit further comprises a third transistor having a first electrode and a second electrode and a control electrode controlling current flowing between said first and second electrodes, said first electrode of said third transistor being connected to said second port, said control electrode of said third transistor being connected to an input terminal of said inverter circuit, said second electrode of said third transistor being coupled to a first voltage, wherein said first port receives a second voltage higher than that of said first voltage, and wherein a current-voltage characteristic between said first port and said second port exhibits a negative resistance function.
Claim 8
Dependent Claim
291 words
An inverter circuit, comprising: a negative resistance circuit including: first and second enhancement FETs each having a first electrode and a second electrode and a gate electrode controlling current flowing between said first and second electrodes, a conductivity type of said first enhancement FET being the same as a conductivity type of said second enhancement FET; a load element having first and second ends wherein said first end is connected to said first enhancement FET and said second end is connected to a first port of said negative resistance circuit, whereby said load element and said first enhancement FET form a first branch connected between said first port and a second port of said negative resistance circuit, said first and second electrodes of said second enhancement FET being connected between said first and second ports to form a second branch parallel to said first branch, said gate electrode of said second enhancement FET being connected to said second electrode of said first enhancement FET; and means for maintaining a constant voltage between said gate electrode of said first enhancement FELT and said first port, and wherein said inverter circuit further comprises a third transistor having a first electrode and a second electrode and a control electrode controlling current flowing between said first and second electrodes, said first electrode of said third transistor being connected to said second port, said control electrode of said third transistor being connected to an input terminal of said inverter circuit, said second electrode of said third transistor being coupled to a first voltage, wherein said first port receives a second voltage higher than that of said first voltage, and wherein a current-voltage characteristic between said first port and said second port exhibits a negative resistance function.
Claim 9
Dependent Claim
183 words
A circuit comprising: first and second enhancement FETs each having a first electrode and a second electrode and a gate electrode controlling current flowing between said first and second electrodes; a load element having first and second ends, wherein said first end is connected to said first enhancement FET and said second end is connected to a first port of said negative resistance circuit, whereby said load element and said first enhancement FET form a first branch connected between said first port and a second port of said circuit, said first and second electrodes of said second enhancement FET being connected between said first and second ports to form a second branch parallel to said first branch, said gate electrode of said second enhancement FET being connected to said second electrode of said first enhancement FET; and means for maintaining a constant voltage between said gate electrode of said first enhancement FET and said first port, said first and second ports receiving first and second voltages, wherein a current-voltage characteristic between said first port and said second port exhibits a negative resistance function.
Claim 10
Dependent Claim
183 words
A circuit comprising: first and second enhancement FETs each having a first electrode and a second electrode and a gate electrode controlling current flowing between said first and second electrodes; a load element having first and second ends, wherein said first end is connected to said first enhancement FET and said second end is connected to a first port of said negative resistance circuit, whereby said load element and said first enhancement FET form a first branch connected between said first port and a second port of said circuit, said first and second electrodes of said second enhancement FET being connected between said first and second ports to form a second branch parallel to said first branch, said gate electrode of said second enhancement FET being connected to said second electrode of said first enhancement FET; and means for maintaining a constant voltage between said gate electrode of said first enhancement FET and said first port, said first and second ports receiving first and second voltages, wherein a current-voltage characteristic between said first port and said second port exhibits a negative resistance function.
Claim 11
Dependent Claim
27 words
A circuit according to claim 7, wherein a conductivity type of said first enhancement FET is the same as a conductivity type of said second enhancement FET.
Claim 12
Dependent Claim
37 words
A circuit according to claim 7, wherein said gate electrode of said first enhancement FET is connected to a control port of said circuit for controlling said current-voltage characteristic between said first port and said second port.
Claim 13
Dependent Claim
21 words
A circuit according to claim 8, wherein each of said first and second enhancement FETs comprises an N-channel type enhancement FET.
Claim 14
Dependent Claim
13 words
A circuit according to claim 8, wherein said load element comprises a FET.
Claim 15
Dependent Claim
16 words
A circuit according to claim 11, wherein said load element comprises a depletion mode load element.
Claim 16
Dependent Claim
25 words
A circuit according to claim 1, wherein said first and second electrodes of said second FET are directly connected to the first and second ports.
Claim 17
Dependent Claim
25 words
A circuit according to claim 7, wherein said first and second electrodes of said second FET are directly connected to the first and second ports.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |