US4575859A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Receiver for digital signals
Assignee: AT&T Teletype Corp
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Filing: 1984-03-23
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Granted: 1986-03-11
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Expires: 2004-03-23
Abstract
Abstract A digital receiver (40) includes a differential amplifier (42) providing data signal E and a control signal F. The level of the control signal F is related to the average level of the data signal E. A slicing circuit 44 includes series connected transistors (46, 48), the gates of which receive the data signal E. A third transistor (52) is connected to provide hysteresis to the slicing circuit, and a fifth transistor (54) is connected in parallel with the third transistor (52). The control electrode of the transistor (52) receives the control signal F from the differential amplifier (42).
Inventors
- 👤 Gary B. Ollendick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:41
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565; H03K5/00; H03K5/01; H03K5/08
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
243 words
A receiver for digital signals comprising: a differential amplifier (42) receiving a digital signal and providing first (E) and second (F) output signals, said first output signal (E) varying in relation to said digital signal and said second output signal (F) being related to the average level of said first output signal (E); a slicing circuit (44) having first and second input transistors (46, 48) with the control electrodes of said first and second transistors (46, 48) commonly connected to said first output signal E from said differential amplifier (42), one electrode of said first transistor (46) being connected to a first terminal of a supply source and one electrode of said second transistor (48) being connected through a load device (50) to a second terminal of said supply source, and the remaining electrodes of said first and second transistors (46, 48) being connected together to provide a control node (55); a third transistor (52) connected across said control node (55) and said second supply source terminal, the control electrode of said third transistor (52) being connected to the junction of said load device (50) and said second transistor (48), said control electrode of said third transistor providing a data output signal (H); and a means (54) connected between said second power source terminal and said control node (55) and responsive to said second output signal (F) of said differential amplifier (42) for influencing the voltage level (G) of said control node (55).
Claim 2
Dependent Claim
243 words
A receiver for digital signals comprising: a differential amplifier (42) receiving a digital signal and providing first (E) and second (F) output signals, said first output signal (E) varying in relation to said digital signal and said second output signal (F) being related to the average level of said first output signal (E); a slicing circuit (44) having first and second input transistors (46, 48) with the control electrodes of said first and second transistors (46, 48) commonly connected to said first output signal E from said differential amplifier (42), one electrode of said first transistor (46) being connected to a first terminal of a supply source and one electrode of said second transistor (48) being connected through a load device (50) to a second terminal of said supply source, and the remaining electrodes of said first and second transistors (46, 48) being connected together to provide a control node (55); a third transistor (52) connected across said control node (55) and said second supply source terminal, the control electrode of said third transistor (52) being connected to the junction of said load device (50) and said second transistor (48), said control electrode of said third transistor providing a data output signal (H); and a means (54) connected between said second power source terminal and said control node (55) and responsive to said second output signal (F) of said differential amplifier (42) for influencing the voltage level (G) of said control node (55).
Claim 3
Dependent Claim
45 words
The circuit of claim 1 wherein said influencing means comprises: a fourth transistor (54) connected between said second power source terminal and said control node (55), the control electrode of said fourth transistor (54) is connected to said second output of said differential amplifier (42).
Claim 4
Dependent Claim
81 words
The circuit of claim 2 wherein said fourth transistor (54) is controlled by said second output signal (F) and said fourth transistor (54) controls the voltage (G) at said control node (55) directly in proportion to the level of said second control signal (F) so that the voltage differential between said first control signal (E) and the signal (G) at said control node (55) is relatively constant over the anticipated variations in the average level of said first control signal (E).
Claim 5
Dependent Claim
16 words
The circuit of claim 3 wherein said load device (50) is implemented by a biased transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-10 | 1989-09-09 | 1990-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-10 | 1993-09-09 | 1994-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-10 | 1997-09-09 | 1998-03-11 | $7700.00 | Window Closed / Lapsed |