US5530884A — System with plurality of datapaths having dual-po…

Claim 1

Independent Claim 282 words

An apparatus for processing data, comprising: (a) global memory means; (b) a plurality of datapaths, each datapath comprising: datapath processing means for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions; local memory means; global port means for transferring data between the local memory means and the global memory means; and dual port means comprising first and second local port means for transferring data between the local memory means and the datapath processing means, wherein the first and second local port means permit simulataneous transfer of data between the local memory means and the datapath processing means; (c) data bus means coupled to the global memory means for transferring data to and from the global memory means; (d) transfer controller means connected to the plurality of data paths and to the global memory means for controlling block transfer and scalar data transfers between the local memory means and the global memory means over the data bus means; and (e) statistical decoder input channel means, comprising: input means for prefetching variable length encoded data from said variable length encoded data source, which comprises a second memory means for storing a plurality of variable length encoded bit sequences, in response to a request by a program running on said processing means of said one of said datapaths of the plurality of datapaths, wherein the variable length encoded data source is the global memory means; statistical decoder processor means and memory means for decoding and converting the variable length encoded data to provide fixed length decoded data; and transmission output means for transmitting the fixed length decoded data to the plurality of datapaths.

Claim 2

Independent Claim 282 words

An apparatus for processing data, comprising: (a) global memory means; (b) a plurality of datapaths, each datapath comprising: datapath processing means for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions; local memory means; global port means for transferring data between the local memory means and the global memory means; and dual port means comprising first and second local port means for transferring data between the local memory means and the datapath processing means, wherein the first and second local port means permit simulataneous transfer of data between the local memory means and the datapath processing means; (c) data bus means coupled to the global memory means for transferring data to and from the global memory means; (d) transfer controller means connected to the plurality of data paths and to the global memory means for controlling block transfer and scalar data transfers between the local memory means and the global memory means over the data bus means; and (e) statistical decoder input channel means, comprising: input means for prefetching variable length encoded data from said variable length encoded data source, which comprises a second memory means for storing a plurality of variable length encoded bit sequences, in response to a request by a program running on said processing means of said one of said datapaths of the plurality of datapaths, wherein the variable length encoded data source is the global memory means; statistical decoder processor means and memory means for decoding and converting the variable length encoded data to provide fixed length decoded data; and transmission output means for transmitting the fixed length decoded data to the plurality of datapaths.

Claim 3

Dependent Claim 32 words

The apparatus of claim 1, wherein the statistical decoder processor means, the transmission output means, and each datapath processing means of the plurality of datapaths are formed in a single integrated circuit.

Claim 4

Dependent Claim 28 words

The apparatus of claim 1, wherein the request by the program comprises and addressing one of the variable length encoded bit sequence stored in the second memory means.

Claim 5

Dependent Claim 13 words

The apparatus of claim 1, wherein the memory means stores a decoding tree.

Claim 6

Dependent Claim 15 words

The apparatus of claim 4, wherein the decoding tree is a conventional Huffman decoding tree.

Claim 7

Dependent Claim 16 words

The apparatus of claim 1, wherein the fixed length decoded data is a sixteen bit byte.

Claim 8

Dependent Claim 71 words

The apparatus of claim 1, wherein the statistical decoder input channel means has native mode operation means and compatible mode operation means, wherein when the statistical decoder input channel means is in the native mode the statistical decoder input channel means performs conventional Huffman decoding and when the statistical decoder input channel means is in the compatible mode the statistical decoder input channel means performs decoding other than conventional Huffman decoding.

Claim 9

Independent Claim 299 words

A method for processing data, the method comprising: (a) providing a global memory means; (b) providing a plurality of datapaths, each datapath comprising: datapath processing means for executing instruction of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions; local memory means; global port means for transferring data between the local memory means and the global memory means; and dual port means comprising first and second local port means for transferring data between the local memory means and the datapath processing means, wherein the first and second local port means permit simultaneous transfer of data between the local memory means and the datapath processing means; (c) transferring data to and from the global memory means with a data bus means coupled to the global memory means; (d) controlling, with transfer controller means connected to the plurality of data paths and to the global memory means, block transfer and scalar data transfers between the local memory means and the global memory over the data bus means; (e) prefetching, with an input means of a statistical decoder input channel means, variable length encoded data from said variable length encoded data source, which comprises a second memory means for storing a plurality of variable length encoded bit sequences, in response to a request by a program running on said processing means of said one of said datapaths of the plurality of datapaths, wherein the variable length encoded data source is the global memory means; (f) decoding and converting the variable length encoded data with a statistical decoder processor means and memory means of the statistical decoder input channel means to provided fixed length decoded data; and (g) transmitting, with a transmission output means, the fixed length decoded data to the plurality of datapaths.

Claim 10

Independent Claim 299 words

A method for processing data, the method comprising: (a) providing a global memory means; (b) providing a plurality of datapaths, each datapath comprising: datapath processing means for executing instruction of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions; local memory means; global port means for transferring data between the local memory means and the global memory means; and dual port means comprising first and second local port means for transferring data between the local memory means and the datapath processing means, wherein the first and second local port means permit simultaneous transfer of data between the local memory means and the datapath processing means; (c) transferring data to and from the global memory means with a data bus means coupled to the global memory means; (d) controlling, with transfer controller means connected to the plurality of data paths and to the global memory means, block transfer and scalar data transfers between the local memory means and the global memory over the data bus means; (e) prefetching, with an input means of a statistical decoder input channel means, variable length encoded data from said variable length encoded data source, which comprises a second memory means for storing a plurality of variable length encoded bit sequences, in response to a request by a program running on said processing means of said one of said datapaths of the plurality of datapaths, wherein the variable length encoded data source is the global memory means; (f) decoding and converting the variable length encoded data with a statistical decoder processor means and memory means of the statistical decoder input channel means to provided fixed length decoded data; and (g) transmitting, with a transmission output means, the fixed length decoded data to the plurality of datapaths.

Claim 11

Dependent Claim 32 words

The method of claim 8, wherein the statistical decoder processor means, the transmission output means, and each datapath processing means of the plurality of datapaths are formed in a single integrated circuit.

Claim 12

Dependent Claim 28 words

The method of claim 8, wherein the request by the program comprises an address for addressing a variable length encoded bit sequence stored in the second memory means.

Claim 13

Dependent Claim 13 words

The method of claim 8, wherein the memory means stores a decoding tree.

Claim 14

Dependent Claim 15 words

The method of claim 11, wherein the decoding tree is a conventional Huffman decoding tree.

Claim 15

Dependent Claim 16 words

The method of claim 8, wherein the fixed length decoded data is a sixteen bit byte.

Claim 16

Dependent Claim 71 words

The method of claim 8, wherein the statistical decoder input channel means has native mode operation means and compatible mode operation means, wherein when the statistical decoder input channel means is in the native mode the statistical decoder input channel means performs conventional Huffman decoding and when the statistical decoder input channel means is in the compatible mode the statistical decoder input channel means performs decoding other than conventional Huffman decoding.

Claim 17

Independent Claim 321 words

An apparatus for processing data, comprising: (a) a global memory; (b) a plurality of datapaths, each datapath comprising: a datapath processor; a local memory; a global port; and a dual port comprising first and second local ports; (c) a data bus coupled to the global memory; (d) a transfer controller connected to the plurality of datapaths and to the global memory; and (e) a statistical decoder input channel, comprising: an input; a statistical decoder processor and memory; and a transmission output; wherein: the datapath processor of each datapath executes instructions of an instruction sequence and provides a plurality of memory request signal types in accordance with the instructions; the global port of the datapath transfers data between the local memory of the datapath and the global memory; the dual port of the datapath transfers data between the local memory of the datapath and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor; the data bus transfers data to and from the global memory; the transfer controller controls block transfer and scalar data transfers between the local memories of the datapaths and the global memory over the data bus; the input of the statistical decoder input channel prefetches variable length encoded data from a variable length encoded data source, which comprises a second memory, wherein the second memory stores a plurality of variable length encoded bit sequences in response to a request by a program running on the datapath processor of one of said datapaths of the plurality of datapaths, wherein the variable length encoded data source is the global memory; the statistical decoder processor and memory of the statistical decoder input channel decodes and converts the variable length encoded data to provide fixed length decoded data; and the transmission output of the statistical decoder input channel transmits the fixed length decoded data to the plurality of datapaths.

Claim 18

Independent Claim 321 words

An apparatus for processing data, comprising: (a) a global memory; (b) a plurality of datapaths, each datapath comprising: a datapath processor; a local memory; a global port; and a dual port comprising first and second local ports; (c) a data bus coupled to the global memory; (d) a transfer controller connected to the plurality of datapaths and to the global memory; and (e) a statistical decoder input channel, comprising: an input; a statistical decoder processor and memory; and a transmission output; wherein: the datapath processor of each datapath executes instructions of an instruction sequence and provides a plurality of memory request signal types in accordance with the instructions; the global port of the datapath transfers data between the local memory of the datapath and the global memory; the dual port of the datapath transfers data between the local memory of the datapath and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor; the data bus transfers data to and from the global memory; the transfer controller controls block transfer and scalar data transfers between the local memories of the datapaths and the global memory over the data bus; the input of the statistical decoder input channel prefetches variable length encoded data from a variable length encoded data source, which comprises a second memory, wherein the second memory stores a plurality of variable length encoded bit sequences in response to a request by a program running on the datapath processor of one of said datapaths of the plurality of datapaths, wherein the variable length encoded data source is the global memory; the statistical decoder processor and memory of the statistical decoder input channel decodes and converts the variable length encoded data to provide fixed length decoded data; and the transmission output of the statistical decoder input channel transmits the fixed length decoded data to the plurality of datapaths.

Claim 19

Dependent Claim 29 words

The apparatus of claim 15, wherein the statistical decoder processor, the transmission output, and each datapath processor of the plurality of datapaths are formed in a single integrated circuit.

Claim 20

Dependent Claim 29 words

The apparatus of claim 15, wherein the request by the program comprises an address for addressing one of the variable length encoded bit sequences stored in the second memory.

Claim 21

Dependent Claim 12 words

The apparatus of claim 15, wherein the memory stores a decoding tree.

Claim 22

Dependent Claim 15 words

The apparatus of claim 18, wherein the decoding tree is a conventional Huffman decoding tree.

Claim 23

Dependent Claim 16 words

The apparatus of claim 15, wherein the fixed length decoded data is a sixteen bit byte.

Claim 24

Dependent Claim 66 words

The apparatus of claim 15, wherein the statistical decoder input channel has a native mode operation and a compatible mode operation, wherein when the statistical decoder input channel is in the native mode the statistical decoder input channel performs conventional Huffman decoding and when the statistical decoder input channel is in the compatible mode the statistical decoder input channel performs deconding other than conventional Huffman decoding.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-06-25	1999-12-25	2000-06-25	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-06-25	2003-12-25	2004-06-25	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-06-25	2007-12-25	2008-06-25	$7700.00	Window Closed / Lapsed

System with plurality of datapaths having dual-ported local memory architecture for converting prefetched variable length data to fixed length decoded data

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