Sticky bit predictor for floating-point multiplication

Claim 2

A circuit for predicting a sticky bit value when multiplying two numbers comprising: a first trailing zero encoder for determining a number of trailing zeros in a first operand mantissa; a second trailing zero encoder for determining a number of trailing zeros in a second operand mantissa; an adder coupled to receive outputs of said first and second trailing zero encoders and providing a sum of said outputs to determine total number of trailing zeros in both said operand mantissas; a comparing means coupled to said adder for determining if said sum is greater than a predetermined number, wherein determining said sticky bit value.

Claim 3

The circuit of claim 1, wherein said adder is comprised of a carry save adder.

Claim 4

The circuit of claim 2, wherein said comparing means is a carry look-ahead circuit.

Claim 5

The circuit of claim 1, wherein said comparing means is a comparator.

Claim 6

In multiplying a multiplicand operand mantissa and a multiplier operand mantissa to perform a floating-point multiplication operation, a circuit for predicting a value of a sticky bit, which is defined as the OR'ing of bits less significant than the round bit of a product of said two operand mantissas, said circuit comprising: a first trailing zero encoder coupled to accept said multiplicand mantissa for determining a number of trailing zeros in said multiplicand mantissa; a second trailing zero encoder coupled to receive said multiplier mantissa for determining a number of trailing zeros in said multiplier mantissa; an adder coupled to receive outputs of said first and second trailing zero encoders as its input and providing a sum of total number of zeros; a comparing means coupled to said adder for determining if said sum is greater than a constant, wherein determining said sticky bit value.

Claim 7

In multiplying a multiplicand operand mantissa and a multiplier operand mantissa to perform a floating-point multiplication operation, a circuit for predicting a value of a sticky bit, which is defined as the OR'ing of bits less significant than the round bit of a product of said two operand mantissas, said circuit comprising: a first trailing zero encoder coupled to accept said multiplicand mantissa for determining a number of trailing zeros in said multiplicand mantissa; a second trailing zero encoder coupled to receive said multiplier mantissa for determining a number of trailing zeros in said multiplier mantissa; an adder coupled to receive outputs of said first and second trailing zero encoders as its input and providing a sum of total number of zeros; a comparing means coupled to said adder for determining if said sum is greater than a constant, wherein determining said sticky bit value.

Claim 8

The circuit of claim 5, wherein each of said trailing zero encoders is comprised of a plurality of encoders arranged in a plurality of rows, such that each row has at least one encoder, said encoders for determining a least significant bit position of a respective one of said operand mantissas which has a non-zero value and wherein all bits less significant than said least significant non-zero bit has a value of zero.

Claim 9

The circuit of claim 6, wherein encoders of a first row are coupled to accept said respective one of said operand mantissas and provide an output for determining least significant bits of a trailing zero count which provides said number of trailing zeros; encoders of each of said rows being grouped and coupled to encoders of a subsequent row wherein output from each subsequent row encoders provides subsequently more significant bits of said trailing zero count; and an encoder of a last row providing most significant bits of said trailing zero count.

Claim 10

In multiplying a multiplicant operand mantissa and a multiplier operand mantissa to perform a floating-point multiplication operation, a method for predicting a value of a sticky bit, which is defined as the OR'ing of bits less significant than the round bit of a product of said two operand mantissas, comprising the steps of: providing a trailing zero encoder for each of said operand mantissas for determining a number of trailing 0s in its respective operand mantissa;

Claim 11

In multiplying a multiplicant operand mantissa and a multiplier operand mantissa to perform a floating-point multiplication operation, a method for predicting a value of a sticky bit, which is defined as the OR'ing of bits less significant than the round bit of a product of said two operand mantissas, comprising the steps of: providing a trailing zero encoder for each of said operand mantissas for determining a number of trailing 0s in its respective operand mantissa;

Claim 12

inputting a respective operand mantissa to its respective trailing zero encoder; determining in each of said trailing zero encoder a least significant non-zero bit in its respective operand mantissa; providing from each of said trailing zero encoder a count of a number of bits less significant than said least significant non-zero bit, said count being a number of trailing zeros for its respective operand mantissa; adding said number of trailing zeros of said two mantissas to provide a sum; comparing said sum to a constant to determine value of said sticky bit.

Claim 13

inputting a respective operand mantissa to its respective trailing zero encoder; determining in each of said trailing zero encoder a least significant non-zero bit in its respective operand mantissa; providing from each of said trailing zero encoder a count of a number of bits less significant than said least significant non-zero bit, said count being a number of trailing zeros for its respective operand mantissa; adding said number of trailing zeros of said two mantissas to provide a sum; comparing said sum to a constant to determine value of said sticky bit.

Claim 14

The method of claim 8, wherein said adding of said two trailing zero counts and said comparing to a constant is achieved by further including steps of coupling said two trailing zero counts to two inputs of a carry save adder and coupling a constant to a third input of said carry save adder: said carry save adder having a sum and carry outputs as its two outputs; said constant being selected so that the most significant bit of the sum of said two outputs of said carry save adder will have a value of one, if and only if said sticky bit is zero; said two outputs of said carry save adder being coupled to a circuit which determines if the most significant bit of the sum of said two outputs of said carry save adder is one.

Claim 15

The method of claim 9, wherein said circuit for determining if said most significant bit of sum of two outputs of said carry adder is a carry look-ahead circuit.