Method of manufacturing a vertical MOSFET having a gate electrode of polycrystalline silicon

Claim 1

A method of manufacturing a vertical metal-oxide-semiconductor field-effect transistor comprising the steps of: forming an insulating film on a surface of a conductive semiconductor substrate; forming a polycrystalline silicon film on said insulating film; doping said polycrystalline silicon film with an n-type impurity; patterning said polycrystalline silicon film doped with said n-type impurity and said insulating film, thereby producing an n-type polycrystalline silicon gate electrode and a gate insulating film; doping said n-type polycrystalline silicon gate electrode with a p-type impurity, thereby producing a p-type polycrystalline silicon gate electrode on said gate insulating film; wherein said n-type impurity doped into said polycrystalline silicon film acts to prevent said p-type impurity doped into said n-type polycrystalline silicon gate electrode from passing through said gate insulating film into said substrate.

Claim 2

A method of manufacturing a vertical metal-oxide-semiconductor field-effect transistor comprising the steps of: forming an insulating film on a surface of a conductive semiconductor substrate; forming a polycrystalline silicon film on said insulating film; doping said polycrystalline silicon film with an n-type impurity; patterning said polycrystalline silicon film doped with said n-type impurity and said insulating film, thereby producing an n-type polycrystalline silicon gate electrode and a gate insulating film; doping said n-type polycrystalline silicon gate electrode with a p-type impurity, thereby producing a p-type polycrystalline silicon gate electrode on said gate insulating film; wherein said n-type impurity doped into said polycrystalline silicon film acts to prevent said p-type impurity doped into said n-type polycrystalline silicon gate electrode from passing through said gate insulating film into said substrate.

Claim 7

A method of manufacturing a vertical metal-oxide-semiconductor field-effect transistor, said method comprising the steps of: (a) forming an insulating film on a first surface of a p-type semiconductor substrate; (b) forming a polycrystalline silicon film on said insulating film; (c) doping said polycrystalline silicon film with a first n-type impurity; (d) patterning said polycrystalline silicon film doped with said first n-type impurity and said insulating film, thereby producing an n-type polycrystalline silicon gate electrode and a gate insulating film; (e) doping said substrate with a second n-type impurity through a penetrating hole formed in said polycrystalline silicon film doped with said first n-type impurity and said insulating film, thereby forming an n-type base region in said substrate; (f) doping said substrate and said n-type polycrystalline silicon gate electrode with a p-type impurity, thereby forming a p-type source region in said substrate and changing a conductivity type of said n-type polycrystalline silicon gate electrode to a p-type; (g) forming an interlayer insulating film to cover said p-type polycrystalline silicon gate electrode and said gate insulating film; (h) forming a contact hole in said interlayer insulating film; (i) forming a source electrode on said interlayer insulating film to be contacted with said source region through said contact hole of interlayer insulating film; and (j) forming a drain electrode on a second surface of said substrate; wherein said first n-type impurity doped into said polycrystalline silicon film acts to prevent said p-type impurity doped into said n-type polycrystalline silicon gate electrode from passing through said gate insulating film into said substrate.

Claim 8

A method of manufacturing a vertical metal-oxide-semiconductor field-effect transistor, said method comprising the steps of: (a) forming an insulating film on a first surface of a p-type semiconductor substrate; (b) forming a polycrystalline silicon film on said insulating film; (c) doping said polycrystalline silicon film with a first n-type impurity; (d) patterning said polycrystalline silicon film doped with said first n-type impurity and said insulating film, thereby producing an n-type polycrystalline silicon gate electrode and a gate insulating film; (e) doping said substrate with a second n-type impurity through a penetrating hole formed in said polycrystalline silicon film doped with said first n-type impurity and said insulating film, thereby forming an n-type base region in said substrate; (f) doping said substrate and said n-type polycrystalline silicon gate electrode with a p-type impurity, thereby forming a p-type source region in said substrate and changing a conductivity type of said n-type polycrystalline silicon gate electrode to a p-type; (g) forming an interlayer insulating film to cover said p-type polycrystalline silicon gate electrode and said gate insulating film; (h) forming a contact hole in said interlayer insulating film; (i) forming a source electrode on said interlayer insulating film to be contacted with said source region through said contact hole of interlayer insulating film; and (j) forming a drain electrode on a second surface of said substrate; wherein said first n-type impurity doped into said polycrystalline silicon film acts to prevent said p-type impurity doped into said n-type polycrystalline silicon gate electrode from passing through said gate insulating film into said substrate.

Claim 13

A method of manufacturing a vertical metal-oxide-semiconductor field-effect transistor, said method comprising the steps of: (a) forming an insulating film on a first surface of a p-type semiconductor substrate; (b) forming a polycrystalline silicon film on said insulating film; (c) doping said polycrystalline silicon film with a first n-type impurity; (d) doping said n-type polycrystalline silicon film doped with said first n-type impurity with a first p-type impurity wherein the result of step (c) and (d) produces an n-type polycrystalline silicon layer; (e) patterning said n-type polycrystalline silicon layer doped with said first n-type impurity and said first p-type impurity and said insulating film, thereby producing an n-type polycrystalline silicon gate electrode and a gate insulating film; (f) doping said substrate with a second n-type impurity through a penetrating hole formed in said n-type polycrystalline silicon layer doped with said first n-type impurity and said first p-type impurity and said insulating film to form an n-type base region in said substrate; (g) doping said substrate and said n-type polycrystalline silicon gate electrode with a second p-type impurity, thereby forming a p-type source region in said substrate and changing said n-type polycrystalline silicon gate electrode to a p-type polycrystalline silicon gate electrode; (h) forming an interlayer insulating film to cover said p-type polycrystalline silicon gate electrode and said gate insulating film; (i) forming a contact hole in said interlayer insulating film; (j) forming a source electrode on said interlayer insulating film to be contacted with said source region through said contact hole of said interlayer insulating film; and (k) forming a drain electrode on a second surface of said substrate; wherein said first n-type impurity doped into said polycrystalline silicon film acts to prevent said first and second p-type impurities doped into said polycrystalline silicon gate electrode doped with said first n-type impurity from passing through said gate insulating film into said substrate.

Claim 14

A method of manufacturing a vertical metal-oxide-semiconductor field-effect transistor, said method comprising the steps of: (a) forming an insulating film on a first surface of a p-type semiconductor substrate; (b) forming a polycrystalline silicon film on said insulating film; (c) doping said polycrystalline silicon film with a first n-type impurity; (d) doping said n-type polycrystalline silicon film doped with said first n-type impurity with a first p-type impurity wherein the result of step (c) and (d) produces an n-type polycrystalline silicon layer; (e) patterning said n-type polycrystalline silicon layer doped with said first n-type impurity and said first p-type impurity and said insulating film, thereby producing an n-type polycrystalline silicon gate electrode and a gate insulating film; (f) doping said substrate with a second n-type impurity through a penetrating hole formed in said n-type polycrystalline silicon layer doped with said first n-type impurity and said first p-type impurity and said insulating film to form an n-type base region in said substrate; (g) doping said substrate and said n-type polycrystalline silicon gate electrode with a second p-type impurity, thereby forming a p-type source region in said substrate and changing said n-type polycrystalline silicon gate electrode to a p-type polycrystalline silicon gate electrode; (h) forming an interlayer insulating film to cover said p-type polycrystalline silicon gate electrode and said gate insulating film; (i) forming a contact hole in said interlayer insulating film; (j) forming a source electrode on said interlayer insulating film to be contacted with said source region through said contact hole of said interlayer insulating film; and (k) forming a drain electrode on a second surface of said substrate; wherein said first n-type impurity doped into said polycrystalline silicon film acts to prevent said first and second p-type impurities doped into said polycrystalline silicon gate electrode doped with said first n-type impurity from passing through said gate insulating film into said substrate.