Method of producing insulated gate MOSFET employing polysilicon mask

Claim 1

A method for forming an electrical device comprising the steps of: (a) sequentially forming a semiconductor layer of a first conductivity type, a semiconductor well region of a second conductivity type, different from said first conductivity type embedded within and forming a part of a first surface of said semiconductor layer, a gate oxide layer disposed on said first surface, and a polycrystalline semiconductor layer; (b) selectively etching said polycrystalline semiconductor layer so as to leave a central part and peripheral portions thereof intact and to form a window region between said central part and said peripheral portions, said window extending over portions of the semiconductor layer of the first conductivity type and the semiconductor well region; (c) introducing impurities through the window region and treating at high temperature to diffuse the impurities such that the base region of the second conductivity type is formed within the portions of the semiconductor layer of the first conductivity type and the semiconductor well region which are aligned with the window; (d) introducing further impurities through the window region suitable for forming a region of the first conductivity type; (e) forming a resist mask over the peripheral portions of the polycrystalline semiconductor layer which extend to cover a portion of the window, such that a second smaller window is formed between the control part of the polycrystalline semiconductor layer and the resist mask; (f) introducing impurities through the second smaller window suitable for a high impurity density region of the second conductivity type; (g) removing the resist mask, the central part of the polysilicon layer and a central portion of the gate oxide layer; and (h) thermally diffusing the impurities introduced in steps (d) and (f) to form a source region and a high impurity density region.

Claim 2

A method for forming an electrical device comprising the steps of: (a) sequentially forming a semiconductor layer of a first conductivity type, a semiconductor well region of a second conductivity type, different from said first conductivity type embedded within and forming a part of a first surface of said semiconductor layer, a gate oxide layer disposed on said first surface, and a polycrystalline semiconductor layer; (b) selectively etching said polycrystalline semiconductor layer so as to leave a central part and peripheral portions thereof intact and to form a window region between said central part and said peripheral portions, said window extending over portions of the semiconductor layer of the first conductivity type and the semiconductor well region; (c) introducing impurities through the window region and treating at high temperature to diffuse the impurities such that the base region of the second conductivity type is formed within the portions of the semiconductor layer of the first conductivity type and the semiconductor well region which are aligned with the window; (d) introducing further impurities through the window region suitable for forming a region of the first conductivity type; (e) forming a resist mask over the peripheral portions of the polycrystalline semiconductor layer which extend to cover a portion of the window, such that a second smaller window is formed between the control part of the polycrystalline semiconductor layer and the resist mask; (f) introducing impurities through the second smaller window suitable for a high impurity density region of the second conductivity type; (g) removing the resist mask, the central part of the polysilicon layer and a central portion of the gate oxide layer; and (h) thermally diffusing the impurities introduced in steps (d) and (f) to form a source region and a high impurity density region.