Manufacture of mos field effect transistor

Abstract

Abstract PURPOSE:To enable to set the position of contact between a source electrode and a deep diffused region at the accurate central position and thus make gate bias constant by a method wherein the transistor is constituted with a semiconductor substrate as a drain or a source by forming the region of a second conductivity type, the region of a first conductivity type as the source or the drain, and a second polycrystalline semiconductor layer as a gate electrode. CONSTITUTION:An N<-> type epitaxial Si layer 22 is formed on the N<+> type Si semiconductor substrate 21, a gate oxide film 23 is formed by a thermal oxidation method, and then a polycrystalline Si layer 24 is formed thereon by a CVD method. Next, a window 25 is opened by selectively etching the polycrystalline Si layer 24, but a part (center) 24c of the polycrystalline Si layer is left at the center of the window 25. The position of the center 24c is determined by a photo mask pattern. When the shape of the window 25 is an equilateral polygon or a circle, it is located at the center of point symmetry of the window. Arsenic is ion-implanted through the window 25 of the polycrystalline Si layer 24, thus introduced in the epitaxial layer 22, and then an N type diffused region 26 is formed by diffusing an impurity introduced by heat treatment in non-oxidizing (or oxidizing) atmosphere.

Inventors

• 👤 Kazuo Yajima
• 👤 矢島　一夫

Bibliographic Details