Method for manufacturing MOS type semiconductor devices

Claim 1

A method for manufacturing a MOS type semiconductor device comprising the steps of: providing a semiconductor drain layer of a first conductivity type, the semiconductor drain layer having a gate insulating film on a surface thereof; forming a gate electrode on the surface of the semiconductor drain layer, the gate electrode being electrically insulated from the drain layer by the gate insulating film; introducing a second conductivity type impurity into said drain layer to form a base layer of the second conductivity type, said gate electrode masking a portion of said drain layer; forming an insulating layer on the surface of said semiconductor drain layer and on said gate electrode, said insulating layer being of a thickness and having a sidewall of a width parallel to the surface of said drain layer, said thickness being substantially perpendicular to the width; introducing ions of the second conductivity type impurity into said base layer to form a low resisitivity base layer region in said base layer; isotropically etching said insulating layer to reduce the thickness of the insulating layer and the width of the sidewall which overlaps the resultant low resistivity base layer region until the sidewall of said insulating layer no longer overlaps an edge of said low resistivity base layer region; forming a resist mask on a portion of said insulating layer; and introducing ions of the first conductivity type impurity into said base layer to form a source layer, said resist mask and said insulating layer covering said gate electrode masking a portion of said base layer.

Claim 2

A method for manufacturing a MOS type semiconductor device comprising the steps of: providing a semiconductor drain layer of a first conductivity type, the semiconductor drain layer having a gate insulating film on a surface thereof; forming a gate electrode on the surface of the semiconductor drain layer, the gate electrode being electrically insulated from the drain layer by the gate insulating film; introducing a second conductivity type impurity into said drain layer to form a base layer of the second conductivity type, said gate electrode masking a portion of said drain layer; forming an insulating layer on the surface of said semiconductor drain layer and on said gate electrode, said insulating layer being of a thickness and having a sidewall of a width parallel to the surface of said drain layer, said thickness being substantially perpendicular to the width; introducing ions of the second conductivity type impurity into said base layer to form a low resisitivity base layer region in said base layer; isotropically etching said insulating layer to reduce the thickness of the insulating layer and the width of the sidewall which overlaps the resultant low resistivity base layer region until the sidewall of said insulating layer no longer overlaps an edge of said low resistivity base layer region; forming a resist mask on a portion of said insulating layer; and introducing ions of the first conductivity type impurity into said base layer to form a source layer, said resist mask and said insulating layer covering said gate electrode masking a portion of said base layer.

Claim 6

A method for manufacturing a MOS type semiconductor device comprising the steps of: providing a semiconductor drain layer of a first conductivity type, the semiconductor drain layer having a gate insulating film on a surface thereof; forming a gate electrode of a predetermined thickness on the surface of said semiconductor drain layer, the gate electrode being electrically insulated from the drain layer by the gate insulating film; introducing a second conductivity type impurity into said drain layer to form a base layer of the second conductivity type, said gate electrode masking a portion of said drain layer; introducing the second conductivity type impurity into said base layer thereby forming a low resistivity base layer region; isotropically etching said gate electrode to reduce its thickness and to reduce a region of the gate electrode which overlaps an edge of said resultant low resistivity base layer region until said gate electrode no longer overlaps the edge of said low resistivity base layer region; forming a resist mask on a portion of said gate insulation film; and introducing the first conductivity type impurity into said base layer while using said resist mask and said gate electrode to mask a portion of said base layer to form a source layer.

Claim 7

A method for manufacturing a MOS type semiconductor device comprising the steps of: providing a semiconductor drain layer of a first conductivity type, the semiconductor drain layer having a gate insulating film on a surface thereof; forming a gate electrode of a predetermined thickness on the surface of said semiconductor drain layer, the gate electrode being electrically insulated from the drain layer by the gate insulating film; introducing a second conductivity type impurity into said drain layer to form a base layer of the second conductivity type, said gate electrode masking a portion of said drain layer; introducing the second conductivity type impurity into said base layer thereby forming a low resistivity base layer region; isotropically etching said gate electrode to reduce its thickness and to reduce a region of the gate electrode which overlaps an edge of said resultant low resistivity base layer region until said gate electrode no longer overlaps the edge of said low resistivity base layer region; forming a resist mask on a portion of said gate insulation film; and introducing the first conductivity type impurity into said base layer while using said resist mask and said gate electrode to mask a portion of said base layer to form a source layer.