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US4855799A Expired / Lapsed US ⏱️ 0.0 years remaining

Power MOS FET with carrier lifetime killer

Assignee: Toshiba Corp
•
Filing: 1987-12-22
•
Granted: 1989-08-08
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Expires: 2007-12-22
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Abstract

Abstract In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the base region. The diffusion is made through an opening formed in a covering insulator layer. An example of the lifetime killer is platinum and the preferable temperature range for diffusing platinum is not higher than 900° C.

Inventors

  • 👤 Hirohito Tanabe
  • 👤 Yu Ohata
  • 👤 Kazuaki Suzuki
  • 👤 Yukiharu Miwa
  • 👤 Yoshihito Nakayama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 17:41
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D30/60; H10D30/64; H10D30/66; H10D30/668; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10D84/00; H10D84/101; H10D84/141; H10D84/143; H10D84/144; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10P32/18; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513; H10D64/60; H10D64/62

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 208 words
An MOS type field effect transistor comprising: a drain region made of a semiconductor substrate of a first conduction type; a base region of a second conduction type formed within said semiconductor substrate, said base region having a deep portion and a shallow portion; a source region of the first conduction type formed within said base region; a gate insulator layer formed above said base region between said drain region and said source region; a gate electrode formed on said gate insulator layer; a covering insulator layer formed over the surface of said substrate including said gate electrode, an opening being formed in a portion of said covering insulator layer and above a PN diode junction formed by said drain and said deep portion of the base region, said opening being located at a position laterally displaced from said gate electrode; a source electrode connected to a portion of said source region and a portion of said base region through said opening; and a drain electrode connected to said drain region; wherein platinum is diffused as a lifetime killer into the vicinity of said diode junction so that the concentration of platinum in the surface of said base region and said source region below said opening is highest.
Claim 2
Dependent Claim 208 words
An MOS type field effect transistor comprising: a drain region made of a semiconductor substrate of a first conduction type; a base region of a second conduction type formed within said semiconductor substrate, said base region having a deep portion and a shallow portion; a source region of the first conduction type formed within said base region; a gate insulator layer formed above said base region between said drain region and said source region; a gate electrode formed on said gate insulator layer; a covering insulator layer formed over the surface of said substrate including said gate electrode, an opening being formed in a portion of said covering insulator layer and above a PN diode junction formed by said drain and said deep portion of the base region, said opening being located at a position laterally displaced from said gate electrode; a source electrode connected to a portion of said source region and a portion of said base region through said opening; and a drain electrode connected to said drain region; wherein platinum is diffused as a lifetime killer into the vicinity of said diode junction so that the concentration of platinum in the surface of said base region and said source region below said opening is highest.

References Cited (Backward Citations)

JPS54124983A Cited
US4630084A Cited
EP0071276A2 Cited
JPS58191440A Cited
US4656493A Cited
US4466176A Cited
US4620211A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-08-07 1993-02-06 1993-08-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-08-07 1997-02-06 1997-08-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-08-07 2001-02-06 2001-08-08 $7700.00 Window Closed / Lapsed

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