Self-aligned process for fabricating small size DMOS cells and MOS devices obtained by means of said process

Claim 1

A process for fabricating vertical type DMOS devices or integrated VDMOS transistors, comprising the following steps: a) thermally oxidizing the surface of an epitaxially grown silicon layer lightly doped with an impurity of a first type of conductivity, grown on the surface of a slice of monocrystalline semiconductor material; b) depositing a layer of polycrystalline silicon; c) doping said polycrystalline layer; d) thermally oxidizing the surface of said poly­crystalline layer; e) depositing a layer of silicon nitride; f) selectively removing said layers of nitride, oxide and polycrystalline silicon, by anisotropic attack, in correspondence of areas where elementary DMOS cells will be formed; g) implanting atoms of an impurity of a second type of conductivity and diffusing to form body regions whose extremes extend beyond the geometrical projection of the edges of said poly­crystalline silicon layer constituting a gate electrode; h) depositing a layer of silicon oxide from vapor phase having a thickness greater or equal to the total thickness of said superimposed layers of thermal oxide, polycrystalline silicon, thermal oxide and silicon nitride present over portions of the surface of said epitaxially grown layer; i) thermally re-flowing the deposited layer of silicon oxide; j) anisotropically attacking said layer of deposited silicon oxide forming spacers along the edges of said superimposed layers; k) implanting an impurity of said second type of conductivity, said spacers defining the implant window, removing said spacers, and forming, by diffusion, a heavily doped short region entirely contained inside said body region and whose lateral rim coincide substantially with the geometrical projection of the edges of said poly­crystalline silicon layer; l) defining,by masking with photoresist, a central area of contact of short circuit; m) removing the layer of oxide and implanting an impurity of said first type of conductivity utilizing said photoresist and said layer of poly­crystalline silicon as mask, followed by removing the photoresist and diffusing to form heavily doped source regions; and n) repeating steps h, i, and j, for defining the electrical contact openings between a suitable source electrode and said source and short regions.