US4503398A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic gain control circuit
Assignee: Motorola Solutions Inc
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Filing: 1982-12-27
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Granted: 1985-03-05
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Expires: 2002-12-27
Abstract
Abstract An automatic gain control circuit is provided for limiting the positive and negative peaks of an input waveform. A differential pair of PNP transistors are coupled to the collector of an NPN amplifying transistor for activating a limiting means on negative peaks of the input waveform as the amplifying transistor approaches cutoff. On positive peaks, a second emitter of the amplifying transistor acts as a collector drawing electrons injected into the base from the collector. A reverse current through the emitter activates the limiting means. The limiting means is coupled to the input terminal for limiting the positive and negative peaks beyond a predetermined level.
Inventors
- 👤 M. Faheem Akram
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:26
CPC Classifications
H; H04; H04M; H04M1/00; H04M1/60; H04M1/6008; H03; H03G; H03G11/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
109 words
An automatic gain control circuit for limiting the peaks of an input signal comprising: a transistor for amplifying said input signal having a base coupled for receiving said input signal, a collector coupled to an output terminal, and a first emitter coupled to a supply voltage terminal; first means coupled to a second emitter of said transistor for limiting positive peaks of said input signal, said second emitter being positively biased to collect electrons from the base which are injected from the collector when it approaches saturation; and second means coupled to said collector of said transistor and said first means for limiting negative peaks of said input signal.
Claim 2
Dependent Claim
109 words
An automatic gain control circuit for limiting the peaks of an input signal comprising: a transistor for amplifying said input signal having a base coupled for receiving said input signal, a collector coupled to an output terminal, and a first emitter coupled to a supply voltage terminal; first means coupled to a second emitter of said transistor for limiting positive peaks of said input signal, said second emitter being positively biased to collect electrons from the base which are injected from the collector when it approaches saturation; and second means coupled to said collector of said transistor and said first means for limiting negative peaks of said input signal.
Claim 3
Dependent Claim
143 words
A circuit for limiting the positive and negative peaks of an audio waveform having an input terminal for receiving said waveform, and an output terminal, comprising: amplifying means comprising at least one NPN transistor having a first emitter coupled to a supply voltage terminal, a base coupled to said input terminal, and a collector coupled to said output terminal for providing an output signal; detection means coupled to said collector for detecting a predetermined voltage on said collector; and limiting means coupled to said input terminal, a second emitter of said NPN transistor, and said detection means, for limiting said input waveform, said limiting means responsive to said detection means on negative peaks of said waveform, said second emitter being positively biased so as to collect electrons from said base which were injected therein from said collector on positive peaks of said waveform.
Claim 4
Dependent Claim
143 words
A circuit for limiting the positive and negative peaks of an audio waveform having an input terminal for receiving said waveform, and an output terminal, comprising: amplifying means comprising at least one NPN transistor having a first emitter coupled to a supply voltage terminal, a base coupled to said input terminal, and a collector coupled to said output terminal for providing an output signal; detection means coupled to said collector for detecting a predetermined voltage on said collector; and limiting means coupled to said input terminal, a second emitter of said NPN transistor, and said detection means, for limiting said input waveform, said limiting means responsive to said detection means on negative peaks of said waveform, said second emitter being positively biased so as to collect electrons from said base which were injected therein from said collector on positive peaks of said waveform.
Claim 5
Dependent Claim
55 words
The circuit according to claim 2 wherein said detection means comprises: a first PNP transistor having an emitter coupled to said collector of said NPN transistor, and a collector coupled to said limiting means; and a second PNP transistor having a base and a collector both coupled to said base of said first PNP transistor.
Claim 6
Dependent Claim
59 words
The circuit according to claim 2 wherein said limiting means comprises: a third PNP transistor having a base and a collector coupled to said detection means; and a fourth PNP transistor having a base coupled to both said second emitter of said NPN transistor and said base of said third PNP transistor, said collector coupled to said input terminal.
References Cited (Backward Citations)
US4049975A
Cited
US4409495A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-04 | 1988-09-03 | 1989-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-04 | 1992-09-03 | 1993-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-04 | 1996-09-03 | 1997-03-05 | $7700.00 | Window Closed / Lapsed |