US4409495A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Schmitt trigger circuit with low input current
Assignee: Fujitsu Ltd
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Filing: 1981-05-29
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Granted: 1983-10-11
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Expires: 2001-05-29
Abstract
Abstract A Schmitt trigger circuit has an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation. In its input stage there is a multi-emitter transistor, and in its output stage a second transistor. The multi-emitter transistor comprises a first emitter and a second emitter. The first emitter is associated with a switching operation in response to the input voltage applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor through the base of the multi-emitter transistor to the ground. The use of the multi-emitter transistor prevents the input current from increasing greatly as the input voltage falls.
Inventors
- 👤 Hiromu Enomoto
- 👤 Yoshiharu Mitono
- 👤 Yasushi Yasuda
- 👤 Taketo Imaizumi
- 👤 Hiroshi Ohta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:24
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/2893
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
161 words
A Schmitt trigger circuit having an input-voltage hysteresis characteristic, comprising: an input stage comprising a first transistor which is a multi-emitter transistor having first and second emitters, and a first load resistor connected to said first emitter at a node; an output stage comprising a second transistor having a base connected to said second emitter of said first transistor; a first pn junction diode having an anode connected to said node and a cathode connected to the base of said second transistor, for turning on said second transistor by applying a voltage lower than the voltage at said node by the amount of the voltage drop across said first pn junction diode; a third transistor having a collector and an emitter connected to said first pn junction diode, for providing said input-voltage hysteresis characteristic; and a switching circuit, connected to said second and third transistors, for turning on said third transistor in response to a turning on of said second transistor.
Claim 2
Dependent Claim
161 words
A Schmitt trigger circuit having an input-voltage hysteresis characteristic, comprising: an input stage comprising a first transistor which is a multi-emitter transistor having first and second emitters, and a first load resistor connected to said first emitter at a node; an output stage comprising a second transistor having a base connected to said second emitter of said first transistor; a first pn junction diode having an anode connected to said node and a cathode connected to the base of said second transistor, for turning on said second transistor by applying a voltage lower than the voltage at said node by the amount of the voltage drop across said first pn junction diode; a third transistor having a collector and an emitter connected to said first pn junction diode, for providing said input-voltage hysteresis characteristic; and a switching circuit, connected to said second and third transistors, for turning on said third transistor in response to a turning on of said second transistor.
Claim 3
Dependent Claim
41 words
A Schmitt trigger circuit as set forth in claim 1, wherein said first transistor is a multi-emitter pnp type transistor further comprising a base connected for receiving the input voltage of the Schmitt trigger circuit, and a collector connected to ground.
Claim 4
Dependent Claim
29 words
A Schmitt trigger circuit as set forth in claim 2, further comprising a power supply, wherein said first load resistor is connected between said power supply and said node.
Claim 5
Dependent Claim
94 words
A Schmitt trigger circuit as set forth in claim 3, wherein said first pn junction diode comprises an npn transistor having an emitter functioning as said cathode and having a base and a collector which are short-circuited and connected to said node to function as said anode, wherein said third transistor has a collector connected to the collector of said first pn junction diode at said node, and wherein said third transistor has an emitter connected to the emitter of said first pn junction diode and to said second emitter of said first transistor.
Claim 6
Dependent Claim
20 words
A Schmitt trigger circuit as set forth in claim 4, wherein said second and third transistors are npn type transistors.
Claim 7
Dependent Claim
22 words
A Schmitt trigger circuit as set forth in claim 5, wherein said second and third transistors are Schottky barrier clamping type transistors.
Claim 8
Dependent Claim
55 words
A Schmitt trigger circuit as set forth in claim 5 or 6, wherein said switching circuit comprises: a second load resistor connected to said power supply; and a fourth transistor which is an npn transistor having a base connected to said load resistor, and having a collector connected to the base of said third transistor.
Claim 9
Dependent Claim
49 words
A Schmitt trigger circuit as set forth in claim 7, wherein said Schmitt trigger circuit further comprises: a second pn junction diode connected between the emitter of said second transistor and ground; and a third load resistor connected to said power supply and the collector of said second transistor.
Claim 10
Dependent Claim
92 words
A Schmitt trigger circuit as set forth in claim 7, wherein said output stage further comprises: a third load resistor having a first terminal connected to said power supply and having a second terminal; a fifth transistor which is npn transistor having a base connected to the collector of said second transistor, having a collector connected to the emitter of said fourth transistor and to said second terminal of said third load resistor, and having an emitter; and a bias resistor connected to the emitter of said fifth transistor and to ground.
Claim 11
Dependent Claim
54 words
A Schmitt trigger circuit as set forth in claim 9, wherein said output stage further comprises a sixth transistor which is npn transistor having a base connected to the emitter of said fifth transistor, having a collector connected as an output terminal of said Schmitt trigger circuit, and having an emitter connected to ground.
Claim 12
Dependent Claim
155 words
A Schmitt trigger circuit as set forth in claim 5 or 6, wherein said switching circuit comprises: a second load resistor having a first terminal connected to said power supply and having a second terminal; a third load resistor having a first terminal connected to said power supply and having a second terminal; a fourth transistor which is an npn transistor having a collector connected to the base of said third transistor and to the second terminal of said second load resistor, having a base, and having an emitter; said Schmitt trigger circuit further comprising: a second pn junction diode connected to the emitter of said fourth transistor and to ground; a fifth transistor which is an npn transistor having a base connected to said second terminal of said third load resistor, having an emitter connected to the collector of said second transistor, and having a collector connected to the base of said fourth transistor.
Claim 13
Dependent Claim
62 words
A Schmitt trigger circuit as set forth in claim 11, further comprising: a bias resistor connected to ground; and a fourth load resistor having a first terminal connected to said power supply and having a second terminal, wherein said second transistor has a collector connected to the second terminal of said fourth load resistor, and an emitter connected to said bias resistor.
Claim 14
Dependent Claim
55 words
A Schmitt trigger circuit as set forth in claim 12, wherein said output stage further comprises a sixth transistor which is an npn transistor having a base connected to the emitter of said second transistor, having a collector connected as an output terminal of said Schmitt trigger circuit, and having an emitter connected to ground.
References Cited (Backward Citations)
US3868517A
Cited
US4031413A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-10 | 1987-04-11 | 1987-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-10 | 1991-04-11 | 1991-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-10 | 1995-04-11 | 1995-10-11 | $7700.00 | Window Closed / Lapsed |