US4031413A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory circuit
Assignee: Hitachi Ltd
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Filing: 1976-01-02
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Granted: 1977-06-21
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Expires: 1996-01-02
Abstract
Abstract A memory circuit for providing a zero OFF-holding power under the logical control of three inputs comprises a memory cell including a semiconductor element circuit of equivalently four PNPN layer structure and a logical input section including at least one PNP transistor and NPN transistor with the collector of the PNP transistor connected to the base of the NPN transistor. The NPN transistor in the logical input section has its collector connected to the control gate of the memory cell, and logical input signals are applied to the emitter and base of the PNP transistor and the emitter of the NPN transistor in the logical input section, respectively.
Inventors
- 👤 Ichiro Ohhinata
- 👤 Shinzi Okuhara
- 👤 Tetsuo Takeshita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:50
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; H03K3/35; H03K3/352
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
90 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; at least a PNP transistor and an NPN transistor, the PNP transistor being connected at its collector to the base of the NPN transistor, the NPN transistor being connected at its collector to the control gate of the semiconductor element circuit, whereby the emitter and base of the PNP transistor and the emitter of the NPN transistor function as logical input terminals, respectively.
Claim 2
Dependent Claim
90 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; at least a PNP transistor and an NPN transistor, the PNP transistor being connected at its collector to the base of the NPN transistor, the NPN transistor being connected at its collector to the control gate of the semiconductor element circuit, whereby the emitter and base of the PNP transistor and the emitter of the NPN transistor function as logical input terminals, respectively.
Claim 3
Dependent Claim
113 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; an NPN transistor; and a resistor, the PNP transistor being connected at its collector to the base of the NPN transistor, the NPN transistor being connected at its collector to the control gate of the semiconductor element circuit, and the resistor being connected at its one end to the base of the NPN transistor and grounded at the other end thereof, whereby the emitter and base of the PNP transistor and the emitter of the NPN transistor function as logical input terminals, respectively.
Claim 4
Dependent Claim
113 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; an NPN transistor; and a resistor, the PNP transistor being connected at its collector to the base of the NPN transistor, the NPN transistor being connected at its collector to the control gate of the semiconductor element circuit, and the resistor being connected at its one end to the base of the NPN transistor and grounded at the other end thereof, whereby the emitter and base of the PNP transistor and the emitter of the NPN transistor function as logical input terminals, respectively.
Claim 5
Dependent Claim
138 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; an NPN transistor; and two resistors, the PNP transistor being connected at its collector to the base of the NPN transistor, the NPN transistor being connected at its collector to the control gate of the semiconductor element circuit, a first one of said two resistors being connected at its one end to the base of the PNP transistor, and the second resistor being connected at one end to the base of the NPN transistor and grounded at the other end thereof, whereby the emitter of the PNP transistor, the other end of the first resistor and the emitter of the NPN transistor function as logical input terminals, respectively.
Claim 6
Dependent Claim
138 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; an NPN transistor; and two resistors, the PNP transistor being connected at its collector to the base of the NPN transistor, the NPN transistor being connected at its collector to the control gate of the semiconductor element circuit, a first one of said two resistors being connected at its one end to the base of the PNP transistor, and the second resistor being connected at one end to the base of the NPN transistor and grounded at the other end thereof, whereby the emitter of the PNP transistor, the other end of the first resistor and the emitter of the NPN transistor function as logical input terminals, respectively.
Claim 7
Dependent Claim
130 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; an NPN transistor; two resistors; and a diode, the PNP transistor being connected at its collector to the base of the NPN transistor and also being connected at its base to a first one of said two resistors through the diode, the NPN transistor being connected at its collector to the control gate of the semiconductor element circuit with the second resistor being connected between the base of the NPN transistor and ground, whereby the emitter of the PNP transistor, the other end of the first resistor and the emitter of the NPN transistor function as logical input terminals, respectively.
Claim 8
Dependent Claim
130 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; an NPN transistor; two resistors; and a diode, the PNP transistor being connected at its collector to the base of the NPN transistor and also being connected at its base to a first one of said two resistors through the diode, the NPN transistor being connected at its collector to the control gate of the semiconductor element circuit with the second resistor being connected between the base of the NPN transistor and ground, whereby the emitter of the PNP transistor, the other end of the first resistor and the emitter of the NPN transistor function as logical input terminals, respectively.
Claim 9
Dependent Claim
115 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; and two NPN transistors, the PNP transistor being connected at its base to the collector of a first one of the NPN transistors and also being connected at its collector to the control gate of the semiconductor element circuit, the first NPN transistor being connected at its emitter to the collector of the second NPN transistor which is grounded at its emitter, whereby the emitter of the PNP transistor, and the bases of the first and second NPN transistors function as logical input terminals, respectively.
Claim 10
Dependent Claim
115 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; and two NPN transistors, the PNP transistor being connected at its base to the collector of a first one of the NPN transistors and also being connected at its collector to the control gate of the semiconductor element circuit, the first NPN transistor being connected at its emitter to the collector of the second NPN transistor which is grounded at its emitter, whereby the emitter of the PNP transistor, and the bases of the first and second NPN transistors function as logical input terminals, respectively.
Claim 11
Dependent Claim
171 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; two NPN transistors; three resistors; and a diode, the PNP transistor being connected at its base to the collector of a first one of said two NPN transistors, at its collector to the control gate of the semiconductor element circuit and at its emitter to one end of a first one of said three resistors, the first NPN transistor being connected at its emitter to the collector of the second one of said two NPN transistors and at its base to one end of a second one of the said three resistors, the base and emitter of the second NPN transistor being connected to one end of a third one of said three resistors through the diode and direct to ground, respectively, whereby the other end of each of said first, second and third resistors function as logical input terminals, respectively.
Claim 12
Dependent Claim
171 words
A memory circuit under the logical control of three inputs, comprising a semiconductor element circuit corresponding to a four layer PNPN structure and having a control gate; a PNP transistor; two NPN transistors; three resistors; and a diode, the PNP transistor being connected at its base to the collector of a first one of said two NPN transistors, at its collector to the control gate of the semiconductor element circuit and at its emitter to one end of a first one of said three resistors, the first NPN transistor being connected at its emitter to the collector of the second one of said two NPN transistors and at its base to one end of a second one of the said three resistors, the base and emitter of the second NPN transistor being connected to one end of a third one of said three resistors through the diode and direct to ground, respectively, whereby the other end of each of said first, second and third resistors function as logical input terminals, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-20 | 1980-12-20 | 1981-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-20 | 1984-12-20 | 1985-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-20 | 1988-12-20 | 1989-06-21 | $7700.00 | Window Closed / Lapsed |