US5164327A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a mis-type semiconductor
Assignee: Fuji Electric Co Ltd
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Filing: 1991-10-08
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Granted: 1992-11-17
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Expires: 2011-10-08
Abstract
Abstract A method of manufacturing an MIS-type semiconductor is disclosed in which an insulation layer is deposited over a semiconductor drain layer of a first conduction type and a contact region of a high concentration second conduction type, a base region of the second conduction type, and a source region of the first conduction type within the base region in the semiconductor drain layer are formed by ion injecting through the insulation layer. Performing the ion injections through the insulation layer prevents ion injection damage to the surface of the drain layer. Furthermore, since the insulation layer is formed prior to the introduction of impurities, which generate high-density crystalline defects, quality degradation in the insulation layer itself can be kept to a minimum.
Inventors
- 👤 Kazumi Maruyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 01:11
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D12/00; H10D12/01; H10D12/031; H10D12/032
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
279 words
A method of manufacturing an MIS-type semiconductor device consisting of: forming a drain layer of a first conduction type on a first surface of a semiconductor substrate of a first conduction type; forming a first insulation layer on the drain layer; forming gate electrodes on the first insulation layer; forming a first mask over the gate electrodes and a portion of the first insulation layer to define a location for a contact region; forming the contact region of a high concentration second conduction type to a first depth within the semiconductor layer by injecting ions through the first insulation layer at the location defined by the first mask and performing an annealing operation after removing the first mask; forming a base region of the second conduction type to a second depth within the semiconductor layer that is less than the first depth by using the gate electrodes as a mask, injecting ions through the first insulation layer and performing an annealing operation; forming a second mask on the first insulation layer between the gate electrodes to define a location for a source region; forming a source region of the first conduction type by injecting ions through the first insulation layer at the location defined by the second mask; removing the second mask; forming a second insulation layer over the gate electrodes and the first insulation layer; forming and opening through the first and second insulation layers to expose parts of the surfaces of the contact region and the source region; forming a source electrode on the exposed surfaces of the contact regions and the source region; and forming a drain electrode on a second surface of the semiconductor substrate.
Claim 2
Independent Claim
279 words
A method of manufacturing an MIS-type semiconductor device consisting of: forming a drain layer of a first conduction type on a first surface of a semiconductor substrate of a first conduction type; forming a first insulation layer on the drain layer; forming gate electrodes on the first insulation layer; forming a first mask over the gate electrodes and a portion of the first insulation layer to define a location for a contact region; forming the contact region of a high concentration second conduction type to a first depth within the semiconductor layer by injecting ions through the first insulation layer at the location defined by the first mask and performing an annealing operation after removing the first mask; forming a base region of the second conduction type to a second depth within the semiconductor layer that is less than the first depth by using the gate electrodes as a mask, injecting ions through the first insulation layer and performing an annealing operation; forming a second mask on the first insulation layer between the gate electrodes to define a location for a source region; forming a source region of the first conduction type by injecting ions through the first insulation layer at the location defined by the second mask; removing the second mask; forming a second insulation layer over the gate electrodes and the first insulation layer; forming and opening through the first and second insulation layers to expose parts of the surfaces of the contact region and the source region; forming a source electrode on the exposed surfaces of the contact regions and the source region; and forming a drain electrode on a second surface of the semiconductor substrate.
Claim 3
Independent Claim
275 words
A method of manufacturing an MIS-type semiconductor device consisting of: forming a drain layer of a first conduction type on a first surface of a semiconductor substrate of a first conduction type; forming a first insulation layer on the drain layer; forming a first mask over selected portions of the first insulation layer to define a location for a contact region; forming the contact region of a high concentration second conduction type to a first depth within the semiconductor layer by injecting ions through the first insulation layer at the location defined by the first mask and performing an annealing operation after removing the first mask; forming gate electrodes on the first insulation layer; forming a base region of the second conduction type to a second depth within the semiconductor layer that is less than the first depth by using the gate electrodes as a mask, injecting ions through the first insulation layer and performing an annealing operation; forming a second mask on the first insulation layer between the gate electrodes to define a location for a source region; forming a source region of the first conduction type by injecting ions through the first insulation layer at the location defined by the second mask; removing the second mask; forming a second insulation layer over the gate electrodes and the first insulation layer; forming and opening through the first and second insulation layers to expose parts of the surfaces of the contact region and the source region; forming a source electrode on the exposed surfaces of the contact regions and the source region; and forming a drain electrode on a second surface of the semiconductor substrate.
Claim 4
Independent Claim
275 words
A method of manufacturing an MIS-type semiconductor device consisting of: forming a drain layer of a first conduction type on a first surface of a semiconductor substrate of a first conduction type; forming a first insulation layer on the drain layer; forming a first mask over selected portions of the first insulation layer to define a location for a contact region; forming the contact region of a high concentration second conduction type to a first depth within the semiconductor layer by injecting ions through the first insulation layer at the location defined by the first mask and performing an annealing operation after removing the first mask; forming gate electrodes on the first insulation layer; forming a base region of the second conduction type to a second depth within the semiconductor layer that is less than the first depth by using the gate electrodes as a mask, injecting ions through the first insulation layer and performing an annealing operation; forming a second mask on the first insulation layer between the gate electrodes to define a location for a source region; forming a source region of the first conduction type by injecting ions through the first insulation layer at the location defined by the second mask; removing the second mask; forming a second insulation layer over the gate electrodes and the first insulation layer; forming and opening through the first and second insulation layers to expose parts of the surfaces of the contact region and the source region; forming a source electrode on the exposed surfaces of the contact regions and the source region; and forming a drain electrode on a second surface of the semiconductor substrate.
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