US5023191A — Method of producing a semiconductor device using …

Claim 1

Independent Claim 220 words

A single mask method for providing multiple masking patterns usable for developing a semiconductor substrate for a semiconductor device, comprising the steps of: (a) forming an etching mask having a first opening exposing an area of an insulative film covering a semiconductor layer; (b) etching said insulative film, via said first opening, to an excessive degree so as to etch said film to a predetermined distance under said masking pattern to form in said film a second opening substantially coextensive with, but larger than, said first opening; (c) etching said semiconductor layer, via said first opening, to form in said layer a third opening substantially coextensive with said first opening; (d) removing said etching mask; (e) etching said semiconductor layer, via said second opening, to an excess degree so as to etch said layer to a predetermined distance under said insulative film to form in said layer a fourth opening substantially coextensive with, but larger than, said second opening; and (f) removing undesired portions of said insulative film to expose said fourth opening; whereby, said first, third, second, and fourth openings are successively usable for etching and ion implantation processes for producing in an underlying semiconductor substrate a plurality of selected conductivity type regions of differing sizes without the need for application of successive masking patterns subject to registration constraints.

Claim 2

Dependent Claim 220 words

A single mask method for providing multiple masking patterns usable for developing a semiconductor substrate for a semiconductor device, comprising the steps of: (a) forming an etching mask having a first opening exposing an area of an insulative film covering a semiconductor layer; (b) etching said insulative film, via said first opening, to an excessive degree so as to etch said film to a predetermined distance under said masking pattern to form in said film a second opening substantially coextensive with, but larger than, said first opening; (c) etching said semiconductor layer, via said first opening, to form in said layer a third opening substantially coextensive with said first opening; (d) removing said etching mask; (e) etching said semiconductor layer, via said second opening, to an excess degree so as to etch said layer to a predetermined distance under said insulative film to form in said layer a fourth opening substantially coextensive with, but larger than, said second opening; and (f) removing undesired portions of said insulative film to expose said fourth opening; whereby, said first, third, second, and fourth openings are successively usable for etching and ion implantation processes for producing in an underlying semiconductor substrate a plurality of selected conductivity type regions of differing sizes without the need for application of successive masking patterns subject to registration constraints.

Claim 3

Dependent Claim 31 words

A single mask method for providing multiple masking patterns usable for developing a semiconductor substrate for a semiconductor device, as in claim 1, in which said etching mask comprises a photoresist.

Claim 4

Dependent Claim 46 words

A single mask method for providing multiple masking patterns usable for developing a semiconductor substrate for a semiconductor device, as in claim 1, in which: the predetermined distance in step (b) is approximately 7-8 microns; and the predetermined distance in step (e) is approximately 0.5 micron.

Claim 5

Dependent Claim 31 words

A single mask method for providing multiple masking patterns usable for developing a semiconductor substrate for a semiconductor device, as in claim 3, in which said etching mask comprises a photoresist.

Claim 6

Dependent Claim 307 words

A single mask method for providing multiple masking patterns useable for developing a semiconductor substrate for a semiconductor device, comprising the steps of: (a) forming an etching mask having a first opening exposing an area of an insulative film covering a semiconductor layer overlaying a film on a semiconductor substrate; (b) etching said insulative film, via said first opening, to an excess degree so as to etch said film to a predetermined distance under said masking pattern to form in said film a second opening substantially coextensive with, but larger than, said first opening; (c) etching said semiconductor layer, via said first opening, to form in said layer a third opening substantially coextensive with said first opening; (d) removing said etching mask; (e) implanting ions, via said third opening, to form a first diffused region in said substrate; (f) etching said semiconductor layer, via said second opening, to an excess degree so as to etch said layer to a predetermined distance under said insulative film to form in said layer a fourth opening substantially coextensive with, but larger than, said second opening; (g) implanting ions, via said second opening, to form a second diffused region in said substrate; (h) increasing the configuration of said first and second diffused regions by drive diffusion; (i) implanting ions, via said second opening, to form a third diffused region in said substrate; and (j) removing undesired portions of said insulative film to expose said fourth opening; (k) implanting ions, via said fourth opening, to form a fourth diffused region in said substrate; whereby, said first, third, second, and fourth openings are successively usable for etching and ion implantation processes for producing in an in an underlying semiconductor substrate a plurality of selected conductivity type regions of differing sizes without the need for application of successive masking patterns subject to registration constraints.

Claim 7

Dependent Claim 307 words

A single mask method for providing multiple masking patterns useable for developing a semiconductor substrate for a semiconductor device, comprising the steps of: (a) forming an etching mask having a first opening exposing an area of an insulative film covering a semiconductor layer overlaying a film on a semiconductor substrate; (b) etching said insulative film, via said first opening, to an excess degree so as to etch said film to a predetermined distance under said masking pattern to form in said film a second opening substantially coextensive with, but larger than, said first opening; (c) etching said semiconductor layer, via said first opening, to form in said layer a third opening substantially coextensive with said first opening; (d) removing said etching mask; (e) implanting ions, via said third opening, to form a first diffused region in said substrate; (f) etching said semiconductor layer, via said second opening, to an excess degree so as to etch said layer to a predetermined distance under said insulative film to form in said layer a fourth opening substantially coextensive with, but larger than, said second opening; (g) implanting ions, via said second opening, to form a second diffused region in said substrate; (h) increasing the configuration of said first and second diffused regions by drive diffusion; (i) implanting ions, via said second opening, to form a third diffused region in said substrate; and (j) removing undesired portions of said insulative film to expose said fourth opening; (k) implanting ions, via said fourth opening, to form a fourth diffused region in said substrate; whereby, said first, third, second, and fourth openings are successively usable for etching and ion implantation processes for producing in an in an underlying semiconductor substrate a plurality of selected conductivity type regions of differing sizes without the need for application of successive masking patterns subject to registration constraints.

Claim 8

Dependent Claim 31 words

A single mask method for providing multiple masking patterns usable for developing a semiconductor substrate for a semiconductor device, as in claim 5, in which said etching mask comprises a photoresist.

Claim 9

Dependent Claim 47 words

A single mask method for providing multiple masking patterns usable for developing a semiconductor substrate for a semiconductor device, as recited in claim 5, in which: the predetermined distance in step (b) is approximately 7-8 microns; and the predetermined distance in step (f) is approximately 0.5 micron.

Claim 10

Dependent Claim 31 words

A single mask method for providing multiple masking patterns usable for developing a semiconductor substrate for a semiconductor device, as in claim 7, in which said etching mask comprises a photoresist.

Claim 11

Independent Claim 301 words

A method of producing a semiconductor device having a semiconductor base layer of a first conductivity type; a first region of a second conductivity type, disposed on the surface of said semiconductor base layer; a second region of said second conductivity type, disposed within said second conductivity type first region and which is diffused more deeply; a third region of said second conductivity type, diffused concentrically with and shallower than either of said first or second regions of said second conductivity type; a first region of said first conductivity type, disposed within said second conductivity type first region bestriding said second conductivity type second and third regions, and diffused shallower than said second conductivity type third region; and an electrode disposed on the surface of the portion of said second conductivity type first region located between said first conductivity type semiconductor base layer and said first conductivity type first region, which comprises: (a) etching an insulation film disposed on a polysilicon by an excessive degree or amount in the planar direction so as to form a predetermined distance between the edges of the outer peripheries of said second conductivity type first and second regions relative to said polysilicon; (b) implanting ions for forming said second conductivity type second region, while using said polysilicon as a mask; (c) etching said polysilicon by an excessive degree or amount in the planar direction such that the shunting resistance portion of said second conductivity type first region, disposed directly under said first conductivity type first region, is the desired length, while using said insulation film as a mask; (d) implanting and diffusing ions for forming said second conductivity type first region; (e) removing said insulation film form said polysilicon; and (f) forming said first conductivity type first region, while using said polysilicon as a mask.

Claim 12

Independent Claim 301 words

A method of producing a semiconductor device having a semiconductor base layer of a first conductivity type; a first region of a second conductivity type, disposed on the surface of said semiconductor base layer; a second region of said second conductivity type, disposed within said second conductivity type first region and which is diffused more deeply; a third region of said second conductivity type, diffused concentrically with and shallower than either of said first or second regions of said second conductivity type; a first region of said first conductivity type, disposed within said second conductivity type first region bestriding said second conductivity type second and third regions, and diffused shallower than said second conductivity type third region; and an electrode disposed on the surface of the portion of said second conductivity type first region located between said first conductivity type semiconductor base layer and said first conductivity type first region, which comprises: (a) etching an insulation film disposed on a polysilicon by an excessive degree or amount in the planar direction so as to form a predetermined distance between the edges of the outer peripheries of said second conductivity type first and second regions relative to said polysilicon; (b) implanting ions for forming said second conductivity type second region, while using said polysilicon as a mask; (c) etching said polysilicon by an excessive degree or amount in the planar direction such that the shunting resistance portion of said second conductivity type first region, disposed directly under said first conductivity type first region, is the desired length, while using said insulation film as a mask; (d) implanting and diffusing ions for forming said second conductivity type first region; (e) removing said insulation film form said polysilicon; and (f) forming said first conductivity type first region, while using said polysilicon as a mask.

Claim 13

Dependent Claim 46 words

A single mask method for providing multiple masking patterns usable for developing a semiconductor substrate for a semiconductor device, as in claim 9, in which: the predetermined distance in step (a) is approximately 7-8 microns; and the predetermined distance in step (c) is approximately 0.5 micron.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-06-10	1994-12-10	1995-06-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-06-10	1998-12-10	1999-06-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-06-10	2002-12-10	2003-06-11	$7700.00	Window Closed / Lapsed

Method of producing a semiconductor device using a single mask method for providing multiple masking patterns

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag