US4889820A
Expired / Lapsed
US
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Method of producing a semiconductor device
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1989-03-09
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Granted: 1989-12-26
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Expires: 2009-03-09
Abstract
Abstract A method of producing a semiconductor device comprises the steps of: preparing a semiconductor substrate, forming a gate insulating layer on the semiconductor substrate, forming a gate electrode on the gate insulating layer, forming a source/drain region in the semiconductor substrate, forming an insulating cover layer on the entire exposed surface, forming a mask on the insulating cover layer having an opening over the gate electrode, implanting one conductivity type impurity ions into the semiconductor substrate through the insulating cover layer, the gate electrode and the gate insulating layer as a first ion implanting process, implanting opposite conductivity type impurity ions into the semiconductor substrate therethrough as a second implanting process, at an implanting angle larger than that used in the first ion implanting process with respect to the normal plane of the semiconductor substrate and to substantially the same depth as the first ion implanting process, and at a dosage smaller than that in the first ion implanting process, whereby the one conductivity type impurity ions at laterally spread portions are compensated.
Inventors
- 👤 Haruhisa Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:06
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; H10P; H10P30/00; H10P30/20; H10P30/22
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
172 words
A method of producing a semiconductor device comprising the steps of: preparing a semiconductor substrate, forming a gate insulating layer on the semiconductor substrate, forming a gate electrode on the gate insulating layer, forming a source/drain region in the semiconductor substrate, forming an insulating cover layer on the entire exposed surface, forming a mask on the insulating cover layer having an opening over the gate electrode, implanting one conductivity type impurity ions into the semiconductor substrate through the insulating cover layer, the gate electrode and the gate insulating layer as a first ion implanting process, implanting opposite conductivity type impurity ions into the semiconductor substrate therethrough as a second implanting process at an implanting angle larger than that of the first ion implanting process with respect to the normal plane of the semiconductor substrate and to substantially the same depth as in the first ion implanting process and at a dosage smaller than in the first ion implanting process, whereby said one conductivity type impurity ions at laterally spread portions are compensated.
Claim 2
Independent Claim
172 words
A method of producing a semiconductor device comprising the steps of: preparing a semiconductor substrate, forming a gate insulating layer on the semiconductor substrate, forming a gate electrode on the gate insulating layer, forming a source/drain region in the semiconductor substrate, forming an insulating cover layer on the entire exposed surface, forming a mask on the insulating cover layer having an opening over the gate electrode, implanting one conductivity type impurity ions into the semiconductor substrate through the insulating cover layer, the gate electrode and the gate insulating layer as a first ion implanting process, implanting opposite conductivity type impurity ions into the semiconductor substrate therethrough as a second implanting process at an implanting angle larger than that of the first ion implanting process with respect to the normal plane of the semiconductor substrate and to substantially the same depth as in the first ion implanting process and at a dosage smaller than in the first ion implanting process, whereby said one conductivity type impurity ions at laterally spread portions are compensated.
Claim 3
Dependent Claim
16 words
A method according to claim 1, wherein said semiconductor substrate is a p type silicon substrate.
Claim 4
Dependent Claim
22 words
A method according to claim 1, wherein said gate electrode is a polycrystalline silicone electrode having a thickness of about 4000 Å.
Claim 5
Dependent Claim
31 words
A method according to claim 1, wherein said insulating cover layer positioned on the entire exposed surface is composed of two phospho-silicate glass layers having a total thickness of 1.1 μm.
Claim 6
Dependent Claim
18 words
A method according to claim 1, wherein said one conductivity type impurity ions are n type impurity ions.
Claim 7
Dependent Claim
18 words
A method according to claim 5, wherein said n type impurity ions are phosphorus ions (P + ).
Claim 8
Dependent Claim
33 words
A method according to claim 1, wherein said one conductivity type impurity ions are implanted at an implanting angle of 0° to 7° with respect to the normal plane of the semiconductor device.
Claim 9
Dependent Claim
36 words
A method according to claim 1, wherein said one conductivity type impurity ions are implanted at a projective range of 0.5 to 3 μm and a dosage of 1 to 5 ×10 13 /cm 2 .
Claim 10
Dependent Claim
18 words
A method according to claim 1, wherein said opposite conductivity type impurity ions are p type impurity ions.
Claim 11
Dependent Claim
18 words
A method according to claim 9, wherein said p type impurity ions are boron ions (B + ).
Claim 12
Dependent Claim
33 words
A method according to claim 1, wherein said opposite conductivity type impurity ions are implanted at an implanting angle of larger than 7° with respect to the normal plane of the semiconductor device.
Claim 13
Dependent Claim
35 words
A method according to claim 1, wherein said opposite conductivity type impurity ions are implanted at a projective range of 0.5 to 3 μm and a dosage of 1 to 5×10 12 /cm 2 .
References Cited (Backward Citations)
US3615875A
Cited
DE2341179A1
Cited
US4382826A
Cited
US4280854A
Cited
GB2056168A
Cited
US4417385A
Cited
JPS59100574A
Cited
JPS61214457A
Cited
US4737471A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-25 | 1993-06-26 | 1993-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-25 | 1997-06-26 | 1997-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-25 | 2001-06-26 | 2001-12-26 | $7700.00 | Window Closed / Lapsed |