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JPH0243740A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of mos semiconductor element

Assignee: Fuji Electric Co Ltd
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Filing: 1988-08-03
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Granted: —
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Expires: 2008-08-03
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Abstract

Abstract PURPOSE:To dispense with a resist coating process for the formation of a resist pattern and a photoetching process by a method wherein an oxide film left on a high-impurity region, which is formed for coming into contact to a source electrode, is used as a mask at the time of ion-implantation for forming source regions in addition to a gate oxide film and gate electrode patterns. CONSTITUTION:A second conductivity type high-impurity concentration region 21 is formed in the surface layer of a first conductivity type drain region (an Si substrate) 1 and thereafter, part of a surface oxide film 41 is made to remain only on a prescribed region of the region 21 and the rest of the film 41 is removed. Then, a second conductivity type channel region 22 is formed. Then, after a gate oxide film and a gate electrode layer are laminated, a patterning of gate electrodes 5 and a gate oxide film 4 under the electrodes 5 is performed leaving said remaining oxide film 41. Then, an ion-implantation for forming first conductivity type source regions 3 is performed using the electrodes 5, the gate oxide film pattern 4 and the remaining oxide film 41 as masks. After that, for example, the surface is covered with a PSG layer 9, a contact hole is formed in a photoetching process and a source electrode 6 is formed.

Inventors

  • 👤 Takeyoshi Nishimura
  • 👤 武義 西村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 05:17
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0291

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