Testability circuits for logic arrays

Claim 2

In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having a defined function which need not be the same as the defined function of other ones of said function circuit modules, each of said function circuit modules having inputs and at least one data output, said at least one data output of at least some of said function circuit modules hardwired to at least one of said inputs of another of said function circuit modules, each of said function circuit modules further including: control means contained within said integrated circuit, responsive to first addressing signals, for directly forcing the data output of any one of said plurality of function circuit modules to assume a selected logic state, said control means being independent of the defined function of and interconnection between said function circuit modules; observe means contained within said integrated circuit, responsive to second addressing signals, for directly observing the data output of any selected one of said function circuit modules at a single I/O pin of said integrated circuit; said control means and said observe means being simultaneously operable.

Claim 3

In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having a define function which need not be the same as the defined function of other ones of said function circuit modules, each of said function circuit modules having inputs and at least one data output, said at least one data output of at least some of said function circuit modules hardwired to at least one of said inputs of another of said function circuit modules, a circuit for providing 100% controllability and observability of said outputs of each of said function circuit modules including: select means for selecting any one of said function circuit modules; control means associated with each of said function circuit modules and responsive to said select means, for directly forcing the data output of any of said function circuit modules to assume a selected logic state, said control means being independent of the defined function of and interconnection between said function circuit modules; and observe means associated with each of said function circuit modules and responsive to said select means, for directly reading the data output of any of said function circuit modules at a single I/O pin of said integrated circuit.

Claim 4

In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having a define function which need not be the same as the defined function of other ones of said function circuit modules, each of said function circuit modules having inputs and at least one data output, said at least one data output of at least some of said function circuit modules hardwired to at least one of said inputs of another of said function circuit modules, a circuit for providing 100% controllability and observability of said outputs of each of said function circuit modules including: select means for selecting any one of said function circuit modules; control means associated with each of said function circuit modules and responsive to said select means, for directly forcing the data output of any of said function circuit modules to assume a selected logic state, said control means being independent of the defined function of and interconnection between said function circuit modules; and observe means associated with each of said function circuit modules and responsive to said select means, for directly reading the data output of any of said function circuit modules at a single I/O pin of said integrated circuit.

Claim 5

In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having a defined function which need not be the same as the defined function of other ones of said function circuit modules, each of said function circuit modules having inputs and at least one data output, said at least one data output of at least some of said function circuit modules hardwired to at least one of said inputs of another of said function circuit modules, a circuit for providing 100% controllability of said outputs of each of said function circuit modules including: a test data input node in each of said function circuit modules in said integrated circuit; addressing means for selecting any one of said function circuit modules; test data path means, directly communicating between an input/output pin of said integrated circuit and each of said test data input nodes of said function circuit modules, for providing a user-selectable logic level present at said input/output pin directly to said test data input nodes of each of said function circuit modules; and control means for directly forcing the data output of the one of said function modules selected by said addressing means to assume a logic state related to said test data, said control means being independent of the defined function of and interconnection between said function circuit modules.

Claim 6

In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having a defined function which need not be the same as the defined function of other ones of said function circuit modules, each of said function circuit modules having inputs and at least one data output, said at least one data output of at least some of said function circuit modules hardwired to at least one of said inputs of another of said function circuit modules, a circuit for providing 100% controllability of said outputs of each of said function circuit modules including: a test data input node in each of said function circuit modules in said integrated circuit; addressing means for selecting any one of said function circuit modules; test data path means, directly communicating between an input/output pin of said integrated circuit and each of said test data input nodes of said function circuit modules, for providing a user-selectable logic level present at said input/output pin directly to said test data input nodes of each of said function circuit modules; and control means for directly forcing the data output of the one of said function modules selected by said addressing means to assume a logic state related to said test data, said control means being independent of the defined function of and interconnection between said function circuit modules.

Claim 7

In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having a defined function which need not be the same as the defined function of other ones of said function circuit modules, each of said function circuit modules having inputs and at least one data output, said at least one data output of at least some of said function circuit modules hardwired to at least one of said inputs of another of said function circuit modules, a circuit for providing 100% controllability and 100% observability of said data outputs of each of said function circuit modules including: a test data input node in each of said function circuit modules contained in said integrated circuit; addressing means for selecting any one of said function circuit modules; test data path means, directly communicating between an input/output pin of said integrated circuit and said test data input nodes of each of said function circuit modules, for providing a user-selectable logic level present at said input/output pin directly to said test data input nodes of each of said function circuit modules; means for directly forcing the data output of the one of said function modules selected by said addressing means to assume an output state related to said test data, and control means for reading the output state of the one of said function circuit modules selected by said addressing means directly to an input/output pin of said integrated circuit, said control means being independent of the defined function of and interconnection between said function circuit modules.

Claim 8

In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having a defined function which need not be the same as the defined function of other ones of said function circuit modules, each of said function circuit modules having inputs and at least one data output, said at least one data output of at least some of said function circuit modules hardwired to at least one of said inputs of another of said function circuit modules, a circuit for providing 100% controllability and 100% observability of said data outputs of each of said function circuit modules including: a test data input node in each of said function circuit modules contained in said integrated circuit; addressing means for selecting any one of said function circuit modules; test data path means, directly communicating between an input/output pin of said integrated circuit and said test data input nodes of each of said function circuit modules, for providing a user-selectable logic level present at said input/output pin directly to said test data input nodes of each of said function circuit modules; means for directly forcing the data output of the one of said function modules selected by said addressing means to assume an output state related to said test data, and control means for reading the output state of the one of said function circuit modules selected by said addressing means directly to an input/output pin of said integrated circuit, said control means being independent of the defined function of and interconnection between said function circuit modules.

Claim 9

In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having a defined function which need not be the same as the defined function of other ones of said function circuit modules, each of said function circuit modules having inputs and at least one data output, said at least one data output of at least some of said function circuit modules hardwired to at least one of said inputs of another of said function circuit modules, a circuit for providing 100% controllability of the outputs of each of said function circuit modules including: means associated with each one of said function circuit modules for isolating its output from its inputs; and means for latching a user-selectable logic level at the data output of each of said function circuit modules.

Claim 10

In an integrated circuit including a plurality of function circuit modules, each of said function circuit modules having a defined function which need not be the same as the defined function of other ones of said function circuit modules, each of said function circuit modules having inputs and at least one data output, said at least one data output of at least some of said function circuit modules hardwired to at least one of said inputs of another of said function circuit modules, a circuit for providing 100% controllability of the outputs of each of said function circuit modules including: means associated with each one of said function circuit modules for isolating its output from its inputs; and means for latching a user-selectable logic level at the data output of each of said function circuit modules.

Claim 11

An integrated circuit including: an array of identical logic function circuits which may be mask programmed to perform any one of a plurality of combinatorial and sequential logic functions, each of said logic function circuits having inputs and at least one output, said integrated circuit configured to mask programmably connect said logic function circuits to each other in a random fashion; logic state input means, directly coupled between an input/output pin on said integrated circuit and a test data input node in each of said logic function circuits, for presenting a user-selectable logic state to each one of said logic function circuits; latching means in each one of said logic function circuits, coupled to said test data input nodes thereof and responsive to a latching signal, for latching said user-selectable logic state into its logic function circuit; selection means, coupled to each of said logic function circuits and responsive to signals from off of said integrated circuit, for providing said latching signal to any one of said logic function circuits; and means for selectively driving said output of each of said logic function circuits to a logic state related to said user-selectable logic state stored in said latching means; whereby each of said logic function circuits may be individually and directly controlled.

Claim 12

An integrated circuit including: an array of identical logic function circuits which may be mask programmed to perform any one of a plurality of combinatorial and sequential logic functions, each of said logic function circuits having inputs and at least one output, said integrated circuit configured to mask programmably connect said logic function circuits to each other in a random fashion; logic state input means, directly coupled between an input/output pin on said integrated circuit and a test data input node in each of said logic function circuits, for presenting a user-selectable logic state to each one of said logic function circuits; latching means in each one of said logic function circuits, coupled to said test data input nodes thereof and responsive to a latching signal, for latching said user-selectable logic state into its logic function circuit; selection means, coupled to each of said logic function circuits and responsive to signals from off of said integrated circuit, for providing said latching signal to any one of said logic function circuits; and means for selectively driving said output of each of said logic function circuits to a logic state related to said user-selectable logic state stored in said latching means; whereby each of said logic function circuits may be individually and directly controlled.