Dimple-free tungsten etching back process

Claim 1

A method of forming a dimple-free tungsten plug in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; etching an opening through said insulating layer to contact one of said semiconductor device structures; depositing a layer of tungsten overlying said insulating layer and within said opening; coating said tungsten layer with a layer of spin-on-glass wherein said spin-on-glass layer planarizes the top surface of said substrate; and etching back said spin-on-glass layer and said tungsten layer leaving said tungsten layer only within said opening as a tungsten plug wherein said spin-on-glass and said tungsten layers are etched using an etching recipe with a selectivity of tungsten to spin-on-glass of between about 1.4 to 1.8 and wherein the presence of said spin-on-glass layer overlying said tungsten layer prevents the formation of a dimple within said tungsten plug completing the formation of said dimple-free tungsten plug in said fabrication of said integrated circuit.

Claim 2

A method of forming a dimple-free tungsten plug in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; etching an opening through said insulating layer to contact one of said semiconductor device structures; depositing a layer of tungsten overlying said insulating layer and within said opening; coating said tungsten layer with a layer of spin-on-glass wherein said spin-on-glass layer planarizes the top surface of said substrate; and etching back said spin-on-glass layer and said tungsten layer leaving said tungsten layer only within said opening as a tungsten plug wherein said spin-on-glass and said tungsten layers are etched using an etching recipe with a selectivity of tungsten to spin-on-glass of between about 1.4 to 1.8 and wherein the presence of said spin-on-glass layer overlying said tungsten layer prevents the formation of a dimple within said tungsten plug completing the formation of said dimple-free tungsten plug in said fabrication of said integrated circuit.

Claim 11

A method of metallization in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; etching an opening through said insulating layer to contact one of said semiconductor device structures; depositing a layer of tungsten overlying said insulating layer and within said opening; coating said tungsten layer with a layer of spin-on-glass wherein said spin-on-glass layer planarizes the top surface of said substrate; etching back said spin-on-glass layer and said tungsten layer leaving said tungsten layer only within said opening as a tungsten plug wherein said spin-on-glass and said tungsten layers are etched using an etching recipe with a selectivity of tungsten to spin-on-glass of between about 1.4 to 1.8 and wherein the presence of said spin-on-glass layer overlying said tungsten layer prevents the formation of a dimple within said tungsten plug; depositing a metal layer overlying said tungsten plug and the top surface of said substrate and patterning said metal layer; and depositing a passivation layer overlying said patterned metal layer completing said metallization in said fabrication of said integrated circuit.

Claim 12

A method of metallization in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; etching an opening through said insulating layer to contact one of said semiconductor device structures; depositing a layer of tungsten overlying said insulating layer and within said opening; coating said tungsten layer with a layer of spin-on-glass wherein said spin-on-glass layer planarizes the top surface of said substrate; etching back said spin-on-glass layer and said tungsten layer leaving said tungsten layer only within said opening as a tungsten plug wherein said spin-on-glass and said tungsten layers are etched using an etching recipe with a selectivity of tungsten to spin-on-glass of between about 1.4 to 1.8 and wherein the presence of said spin-on-glass layer overlying said tungsten layer prevents the formation of a dimple within said tungsten plug; depositing a metal layer overlying said tungsten plug and the top surface of said substrate and patterning said metal layer; and depositing a passivation layer overlying said patterned metal layer completing said metallization in said fabrication of said integrated circuit.

Claim 27

A method of metallization in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; etching an opening through said insulating layer to contact one of said semiconductor device structures; depositing an adhesion layer overlying said insulating layer and within said opening; depositing a layer of tungsten overlying said adhesion layer; coating said tungsten layer with a layer of spin-on-glass wherein said spin-on-glass layer planarizes the top surface of said substrate; etching back said spin-on-glass layer and said tungsten layer leaving said tungsten layer only within said opening as a tungsten plug wherein said spin-on-glass and said tungsten layers are etched using an etching recipe with a selectivity of tungsten to spin-on-glass of between about 1.4 to 1.8 and wherein the presence of said spin-on-glass layer overlying said tungsten layer prevents the formation of a dimple within said tungsten plug wherein said tungsten plug has a bump-like profile; depositing a metal layer overlying said tungsten plug and the top surface of said substrate and patterning said metal layer; and depositing a passivation layer overlying said patterned metal layer completing said metallization in said fabrication of said integrated circuit.

Claim 28

A method of metallization in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; etching an opening through said insulating layer to contact one of said semiconductor device structures; depositing an adhesion layer overlying said insulating layer and within said opening; depositing a layer of tungsten overlying said adhesion layer; coating said tungsten layer with a layer of spin-on-glass wherein said spin-on-glass layer planarizes the top surface of said substrate; etching back said spin-on-glass layer and said tungsten layer leaving said tungsten layer only within said opening as a tungsten plug wherein said spin-on-glass and said tungsten layers are etched using an etching recipe with a selectivity of tungsten to spin-on-glass of between about 1.4 to 1.8 and wherein the presence of said spin-on-glass layer overlying said tungsten layer prevents the formation of a dimple within said tungsten plug wherein said tungsten plug has a bump-like profile; depositing a metal layer overlying said tungsten plug and the top surface of said substrate and patterning said metal layer; and depositing a passivation layer overlying said patterned metal layer completing said metallization in said fabrication of said integrated circuit.