Patent US5524256A successfully refreshed from Google Patents.
US5524256A
Expired / Lapsed
US
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Method and system for reordering bytes in a data stream
Assignee: Apple Inc
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Filing: 1993-05-07
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Granted: 1996-06-04
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Expires: 2013-05-07
Abstract
Abstract A method and system are disclosed for efficiently translating data from one known data sequencing arrangement to an alternative sequencing arrangement. The method consists of the steps of generating a source sequence signal which identifies the ordering of units within the source sequence, generating a destination sequence signal which identifies the ordering of units within the destination sequence, and combining the source signal and destination signal to produce a permutation signal which defines the relationship between the source sequence and the destination sequence. Once the permutation signal has been defined, this permutation signal is applied to the source sequence to allow the reordering of the source sequence into the desired destination sequence. A reordering circuit is used to rearrange the source sequence units into the desired destination sequence units utilizing the permutation signal generated in the present invention. The reordering circuit consists of an array of ordered swap units which contain inputs for source sequence signals and permutation signals, and outputs which propagate destination sequences.
Inventors
- 👤 Kenneth E. Turkowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:38
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/768; G06F7/762; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30025; G06F9/30032
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
351 words
A computer implemented method for translating a source sequence of ordered data units into a destination sequence having a different ordering of said data units, comprising the computer implemented steps of: generating a source sequence signal, E S , which identifies the ordering of units within the source sequence; generating a destination sequence signal, E D , which identifies the ordering of units within the destination sequence; combining the source sequence signal and the destination sequence signal to produce a permutation signal, E S , according to the formula: E.sub.P =(E.sub.S XOR E.sub.D) AND (n-1) where n is equal to the number of data units to be translated; and reordering the units from the source sequence in response to the permutation signal to produce a translated destination sequence, wherein the data unit is an eight-bit byte, and E S and E D are digital signals which are defined for source and destination sequences, respectively, and are generated by adding together individual signal elements, wherein the individual signal elements are determined from the following relationships: (i) for bytes ordered within a WORD16, the signal element is equal to 01 hex when the ordering is little-endian; (ii) for WORD16's ordered within a WORD32, the signal element is equal to 02 hex when the ordering is little-endian; (iii) for WORD32's ordered within a WORD64, the signal element is equal to 04 hex when the ordering is little-endian; (iv) for WORD64's ordered within a WORD128, the signal element is equal to 08 hex when the ordering is little-endian; (v) for WORD 128's ordered within a WORD256, the signal element is equal to 10 hex when the ordering is little-endian; (vi) for WORD256's ordered within a WORD512, the signal element is equal to 20 hex when the ordering is little-endian; (vii) for WORD512's ordered within a WORD1024, the signal element is equal to 40 hex when the ordering is little-endian; (viii) for WORD 1024's ordered within a WORD2048, the signal element is equal to 80 hex when the ordering is little-endian; and (ix) for orderings which are big-endian, the signal element is equal to 00 hex.
Claim 2
Dependent Claim
351 words
A computer implemented method for translating a source sequence of ordered data units into a destination sequence having a different ordering of said data units, comprising the computer implemented steps of: generating a source sequence signal, E S , which identifies the ordering of units within the source sequence; generating a destination sequence signal, E D , which identifies the ordering of units within the destination sequence; combining the source sequence signal and the destination sequence signal to produce a permutation signal, E S , according to the formula: E.sub.P =(E.sub.S XOR E.sub.D) AND (n-1) where n is equal to the number of data units to be translated; and reordering the units from the source sequence in response to the permutation signal to produce a translated destination sequence, wherein the data unit is an eight-bit byte, and E S and E D are digital signals which are defined for source and destination sequences, respectively, and are generated by adding together individual signal elements, wherein the individual signal elements are determined from the following relationships: (i) for bytes ordered within a WORD16, the signal element is equal to 01 hex when the ordering is little-endian; (ii) for WORD16's ordered within a WORD32, the signal element is equal to 02 hex when the ordering is little-endian; (iii) for WORD32's ordered within a WORD64, the signal element is equal to 04 hex when the ordering is little-endian; (iv) for WORD64's ordered within a WORD128, the signal element is equal to 08 hex when the ordering is little-endian; (v) for WORD 128's ordered within a WORD256, the signal element is equal to 10 hex when the ordering is little-endian; (vi) for WORD256's ordered within a WORD512, the signal element is equal to 20 hex when the ordering is little-endian; (vii) for WORD512's ordered within a WORD1024, the signal element is equal to 40 hex when the ordering is little-endian; (viii) for WORD 1024's ordered within a WORD2048, the signal element is equal to 80 hex when the ordering is little-endian; and (ix) for orderings which are big-endian, the signal element is equal to 00 hex.
Claim 3
Dependent Claim
320 words
A computer system for translating a source sequence of n ordered data units into a desired destination sequence having a different ordering, comprising: means for generating a source sequence signal, E S , which identifies the ordering of units within the source sequence; means for generating a destination sequence signal, E D , which identifies the ordering of units within the destination sequence; means for combining the source sequence signal and destination sequence signal to produce a permutation signal, E P defined by the formula: E P =(E S XOR E D ) AND (n-1); and means for reordering the units from the source sequence in response to the permutation signal to produce a translated destination sequence of data units, wherein E S and E D are generated by adding together individual signal elements, wherein the individual signal elements are determined from the following relationships: (i) for bytes ordered within a WORD16, the signal element is equal to 01 hex when the ordering is little-endian; (ii) for WORD16's ordered within a WORD32, the signal elemem is equal to 02 hex when the ordering is little-endian; (iii) for WORD32's ordered within a WORD64, the signal element is equal to 04 hex when the ordering is little-endian; (iv) for WORD64's ordered within a WORD128, the signal element is equal to 08 hex when the ordering is little-endian; (v) for WORD128's ordered within a WORD256, the signal element is equal to 10 hex when the ordering is little-endian; (vi) for WORD256's ordered within a WORD512, the signal element is equal to 20 hex when the ordering is little-endian; (vii) for WORD512's ordered within a WORD1024, the signal element is equal to 40 hex when the ordering is little-endian; (viii) for WORD1024's ordered within a WORD2048, the signal element is equal to 80 hex when the ordering is little-endian; and (ix) for orderings which are big-endian, the signal element is equal to 00 hex.
Claim 4
Dependent Claim
320 words
A computer system for translating a source sequence of n ordered data units into a desired destination sequence having a different ordering, comprising: means for generating a source sequence signal, E S , which identifies the ordering of units within the source sequence; means for generating a destination sequence signal, E D , which identifies the ordering of units within the destination sequence; means for combining the source sequence signal and destination sequence signal to produce a permutation signal, E P defined by the formula: E P =(E S XOR E D ) AND (n-1); and means for reordering the units from the source sequence in response to the permutation signal to produce a translated destination sequence of data units, wherein E S and E D are generated by adding together individual signal elements, wherein the individual signal elements are determined from the following relationships: (i) for bytes ordered within a WORD16, the signal element is equal to 01 hex when the ordering is little-endian; (ii) for WORD16's ordered within a WORD32, the signal elemem is equal to 02 hex when the ordering is little-endian; (iii) for WORD32's ordered within a WORD64, the signal element is equal to 04 hex when the ordering is little-endian; (iv) for WORD64's ordered within a WORD128, the signal element is equal to 08 hex when the ordering is little-endian; (v) for WORD128's ordered within a WORD256, the signal element is equal to 10 hex when the ordering is little-endian; (vi) for WORD256's ordered within a WORD512, the signal element is equal to 20 hex when the ordering is little-endian; (vii) for WORD512's ordered within a WORD1024, the signal element is equal to 40 hex when the ordering is little-endian; (viii) for WORD1024's ordered within a WORD2048, the signal element is equal to 80 hex when the ordering is little-endian; and (ix) for orderings which are big-endian, the signal element is equal to 00 hex.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-04 | 1999-12-04 | 2000-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-04 | 2003-12-04 | 2004-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-04 | 2007-12-04 | 2008-06-04 | $7700.00 | Window Closed / Lapsed |