US5423010A
Expired / Lapsed
US
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Structure and method for packing and unpacking a stream of N-bit data to and from a stream of N-bit data words
Assignee: LSI Corp
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Filing: 1992-01-24
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Granted: 1995-06-06
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Expires: 2012-01-24
Abstract
Abstract A structure and a method capable of both packing data into and unpacking data from either the little endian or the big endian format are provided. Under the structure and method of the present invention, the packed or unpacked data, as the case may be, is only shifted in one direction. During a packing operation, a stream of n-bit data is packed into a stream of m-bit words. During an unpacking operation, a stream of m-bit packed data is unpacked into a stream of n-bit words. n≦m.
Inventors
- 👤 Toshiaki Mizukami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:53
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/768; G06F5/00; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30025; G06F9/30032; G06F9/30036; G06F9/30038
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
150 words
A structure for packing a stream of n-bit data into a stream of m-bit data words (n≦m) for both little endian and big endian formats, comprising: a 2m-bit register for holding up to 2m bits of packed data; means for shifting in one direction only each of said n-bit data into position for insertion into said 2m-bit register as said packed data, said shifting means shifting each of said n-bit data, under said little endian format, a number of bits equalling the number of bits (modulo m) of said packed data in said 2m-bit register before said insertion, and under said big endian format, a number of bits equalling 2m minus both said number of bits (modulo m) of packed data and n; and means for transferring from said 2m-bit register an m-bit output datum whenever the number of bits of said packed data in said 2m-bit register exceeds m.
Claim 2
Dependent Claim
150 words
A structure for packing a stream of n-bit data into a stream of m-bit data words (n≦m) for both little endian and big endian formats, comprising: a 2m-bit register for holding up to 2m bits of packed data; means for shifting in one direction only each of said n-bit data into position for insertion into said 2m-bit register as said packed data, said shifting means shifting each of said n-bit data, under said little endian format, a number of bits equalling the number of bits (modulo m) of said packed data in said 2m-bit register before said insertion, and under said big endian format, a number of bits equalling 2m minus both said number of bits (modulo m) of packed data and n; and means for transferring from said 2m-bit register an m-bit output datum whenever the number of bits of said packed data in said 2m-bit register exceeds m.
Claim 3
Dependent Claim
61 words
A structure as in claim 1, wherein said 2m-bit register contains a lower order m bits of data and a higher order m bits of data, said transferring means further comprises means for copying said lower order m bits of data in said 2m-bit register to become said higher order m bits of data in said 2m-bit register and vice versa.
Claim 4
Dependent Claim
12 words
A structure as in claim 2, wherein said copying means comprises multiplexors.
Claim 5
Dependent Claim
18 words
A structure as in claim 1, wherein said shifting means comprises a barrel shifter capable only of left-shift.
Claim 6
Dependent Claim
25 words
A structure as in claim 1, wherein said shifting means comprises OR gates for inserting each of said shifted n-bit data into said 2m-bit register.
Claim 7
Dependent Claim
162 words
A structure for unpacking a stream of n-bit data from a stream of m-bit data words for both little endian and big endian formats, comprising: a 2m-bit register for holding as packed data up to two of said m-bit data words at a time; means for shifting in one direction only content of said 2m-bit register, for extraction from predetermined bit positions each of said n-bit data, said shifting means shifting said content of said 2m-bit register, under said little endian format, a number of bits equalling the number of bits (modulo m) of said packed data remaining in said 2m-bit register before said extraction, and under said big endian format, a number of bits equalling 2m minus both said number of bits (modulo m) of packed data and n; means for transferring into said 2m-bit register an m-bit input datum as said packed data whenever the number of bits of said packed data in said 2m-bit register is less than m.
Claim 8
Dependent Claim
162 words
A structure for unpacking a stream of n-bit data from a stream of m-bit data words for both little endian and big endian formats, comprising: a 2m-bit register for holding as packed data up to two of said m-bit data words at a time; means for shifting in one direction only content of said 2m-bit register, for extraction from predetermined bit positions each of said n-bit data, said shifting means shifting said content of said 2m-bit register, under said little endian format, a number of bits equalling the number of bits (modulo m) of said packed data remaining in said 2m-bit register before said extraction, and under said big endian format, a number of bits equalling 2m minus both said number of bits (modulo m) of packed data and n; means for transferring into said 2m-bit register an m-bit input datum as said packed data whenever the number of bits of said packed data in said 2m-bit register is less than m.
Claim 9
Dependent Claim
61 words
A structure as in claim 6, wherein said 2m-bit register contains a lower order m bits of data and a higher order m bits of data, said transferring means further comprises means for copying said lower order m bits of data in said m-bit register to become said higher order m bits of data in said 2m-bit register and vice versa.
Claim 10
Dependent Claim
12 words
A structure as in claim 7, wherein said copying means comprises multiplexors.
Claim 11
Dependent Claim
18 words
A structure as in claim 6, wherein said shifting means comprises a barrel shifter capable only of left-shift.
Claim 12
Dependent Claim
33 words
A structure as in claim 6, wherein said shifting means comprises means for masking selected bits of said 2m-bit register in order to extract each of said n-bit data from said 2m-bit register.
Claim 13
Independent Claim
157 words
A method for packing a stream of n-bit data into a stream of m-bit words for both little endian and big endian formats, comprising the steps: providing a 2m-bit register for holding up to 2m bits of packed data; and repeating in order the steps of: (i) shifting in a one direction-only shifter each of said n-bit data into position for insertion into said 2m-bit register as said packed data, said shifting step shifting each of said n-bit data, under said little endian format, a number of bits equalling the number of bits (modulo m) of said packed data in said 2m-bit register before said insertion, and under said big endian format, a number of bits equalling 2m minus both said number of bits (modulo m) of said packed data and n; and (ii) transferring from said 2m-bit register an m-bit output datum whenever the number of bits of packed data in said 2m-bit register exceeds m.
Claim 14
Independent Claim
157 words
A method for packing a stream of n-bit data into a stream of m-bit words for both little endian and big endian formats, comprising the steps: providing a 2m-bit register for holding up to 2m bits of packed data; and repeating in order the steps of: (i) shifting in a one direction-only shifter each of said n-bit data into position for insertion into said 2m-bit register as said packed data, said shifting step shifting each of said n-bit data, under said little endian format, a number of bits equalling the number of bits (modulo m) of said packed data in said 2m-bit register before said insertion, and under said big endian format, a number of bits equalling 2m minus both said number of bits (modulo m) of said packed data and n; and (ii) transferring from said 2m-bit register an m-bit output datum whenever the number of bits of packed data in said 2m-bit register exceeds m.
Claim 15
Dependent Claim
62 words
A method as in claim 11, wherein said 2m-bit register contains a lower order m bits of data and a higher order m bits of data, said transferring step further comprises the step of copying said lower order m bits of data in said 2m-bit register to become said higher order m bits of data in said 2m-bit register and vice versa.
Claim 16
Dependent Claim
12 words
A method as in claim 12, wherein said copying step uses multiplexors.
Claim 17
Dependent Claim
13 words
A method as in claim 13, wherein said shifting step comprises only left-shifts.
Claim 18
Dependent Claim
29 words
A method as in claim 11, wherein said shifting step comprises the step of using OR gates for inserting each of said shifted n-bit data into said 2m-bit register.
Claim 19
Independent Claim
174 words
A method for unpacking a stream of n-bit data from a stream of m-bit data words (n≦m) for both little endian and big endian formats, comprising the steps of: providing a 2m-bit register for holding as packed data up to two of said m-bit data words at a time; and repeating in order the steps of: (i) transferring into said 2m-bit register an m-bit input datum as said packed data whenever the number of bits of packed data in said 2m-bit register is less than m; and (ii) shifting in a one direction-only shifter content of said 2m-bit register, for extraction from predetermined bit positions each of said n-bit data, said shifting step shifting said content of said 2m-bit register, under said little endian format, a number of bits equalling the number of bits (modulo m) of said packed data remaining in said 2m-bit register before said extraction, and under said big endian format, a number of bits equalling 2m minus both said number of bits (modulo m) of said packed data and n.
Claim 20
Independent Claim
174 words
A method for unpacking a stream of n-bit data from a stream of m-bit data words (n≦m) for both little endian and big endian formats, comprising the steps of: providing a 2m-bit register for holding as packed data up to two of said m-bit data words at a time; and repeating in order the steps of: (i) transferring into said 2m-bit register an m-bit input datum as said packed data whenever the number of bits of packed data in said 2m-bit register is less than m; and (ii) shifting in a one direction-only shifter content of said 2m-bit register, for extraction from predetermined bit positions each of said n-bit data, said shifting step shifting said content of said 2m-bit register, under said little endian format, a number of bits equalling the number of bits (modulo m) of said packed data remaining in said 2m-bit register before said extraction, and under said big endian format, a number of bits equalling 2m minus both said number of bits (modulo m) of said packed data and n.
Claim 21
Dependent Claim
62 words
A method as in claim 16, wherein said 2m-bit register contains a lower order m bits of data and a higher order m bits of data, said transferring step further comprises the step of copying said lower order m bits of data in said 2m-bit register to become said higher order m bits of data in said 2m-bit register and vice versa.
Claim 22
Dependent Claim
13 words
A method as in claim 17, wherein said copying step is uses multiplexors.
Claim 23
Dependent Claim
13 words
A method as in claim 16, wherein said shifting step comprises only left-shifts.
Claim 24
Dependent Claim
35 words
A method as in claim 16, wherein said shifting step comprises the step of masking selected bits of said 2m-bit register in order to extract each of said n-bit of data from said 2m-bit register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-05 | 1998-12-05 | 1999-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-05 | 2002-12-05 | 2003-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-05 | 2006-12-05 | 2007-06-06 | $7700.00 | Window Closed / Lapsed |