US5398328A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders
Assignee: MIPS Tech LLC
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Filing: 1993-09-27
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Granted: 1995-03-14
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Expires: 2013-09-27
Abstract
Abstract A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte address in the other architecture. The conversion method and apparatus is implemented in hardware by setting a bit in a status register indicating a Big Endian or Little Endian architecture in conjunction with an XOR gate which couples the byte address to binary 3. The conversion method and apparatus is implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and XORing the two least significant bits of the byte address with a binary 3.
Inventors
- 👤 Larry B. Weber
- 👤 Earl A. Killian
- 👤 Mark I. Himelstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:16
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/768; G06F9/00; G06F9/06; G06F9/30; G06F9/34
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
141 words
A method for converting a program designed to be executed on a computer system employing a first memory order to a program which is executable on a computer system employing a second memory order, the second memory order being the reverse of the first memory order, the method comprising the steps of: (a) finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits; (b) combining the two least significant bits of each byte address with binary three using an exclusive-OR logic function, thereby generating two complementary bits for each byte address; and (c) replacing the two least significant bits of each byte address with the two complementary bits, thereby generating a new byte address for each of said bytes of data.
Claim 2
Independent Claim
141 words
A method for converting a program designed to be executed on a computer system employing a first memory order to a program which is executable on a computer system employing a second memory order, the second memory order being the reverse of the first memory order, the method comprising the steps of: (a) finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits; (b) combining the two least significant bits of each byte address with binary three using an exclusive-OR logic function, thereby generating two complementary bits for each byte address; and (c) replacing the two least significant bits of each byte address with the two complementary bits, thereby generating a new byte address for each of said bytes of data.
Claim 3
Dependent Claim
28 words
The method of claim 1 further comprising the step of detecting whether the program is designed to be executed on a computer system employing the first memory order.
Claim 4
Dependent Claim
20 words
The method of claim 2 further comprising the step of detecting the two least significant bits of each byte address.
Claim 5
Dependent Claim
23 words
The method of claim 1 wherein the first memory order comprises big endian order, and the second memory order comprises little endian order.
Claim 6
Dependent Claim
23 words
The method of claim 1 wherein the first memory order comprises little endian order, and the second memory order comprises big endian order.
Claim 7
Dependent Claim
130 words
A computer system employing a first memory order which converts and executes programs designed to be executed on computer systems employing a second memory order, the second memory order being the reverse of the first memory order, comprising: means for finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits; means for combining the two least significant bits of each byte address with binary three, using an exclusive-OR logic function, thereby generating two complementary bits for each byte address; and means for replacing the two least significant bits of each byte address with the two complementary bits, thereby generating a new byte address for each of said bytes of data.
Claim 8
Dependent Claim
130 words
A computer system employing a first memory order which converts and executes programs designed to be executed on computer systems employing a second memory order, the second memory order being the reverse of the first memory order, comprising: means for finding all instructions in the program which operate on bytes of data, each of said bytes of data having a byte address, each byte address having two least significant bits; means for combining the two least significant bits of each byte address with binary three, using an exclusive-OR logic function, thereby generating two complementary bits for each byte address; and means for replacing the two least significant bits of each byte address with the two complementary bits, thereby generating a new byte address for each of said bytes of data.
Claim 9
Dependent Claim
41 words
The computer system of claim 2 further comprising: means for detecting whether the program is designed to be executed on a computer system employing a second memory order; and means for detecting the two least significant bits of each byte address.
Claim 10
Dependent Claim
24 words
The computer system of claim 2 wherein the first memory order comprises bit endian order, and the second memory order comprises little endian order.
Claim 11
Dependent Claim
24 words
The computer system of claim 2 wherein the first memory order comprises little endian order, and the second memory order comprises big endian order.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |