US5506971A
Expired / Lapsed
US
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Method and apparatus for performing a snoop-retry protocol in a data processing system
Assignee: Apple Inc
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Filing: 1995-02-09
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Granted: 1996-04-09
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Expires: 2015-02-09
Abstract
Abstract A data processing system (10) and method for performing a snoop-retry protocol using an arbiter (14). Multiple bus masters (12, 16, 17) are coupled to multiple shared buses (20, 22, 24, 26). Each bus master (12, 16, 17) may initiate a bus transaction ("initiating master"), or snoop the bus transaction ("snooping bus master") occurring on a shared bus (20). When an initiating processor requests access to a dirty cache line in a memory (18), a snooping bus master asserts a shared address retry (ARTRY*) signal to inform the initiating processor to relinquish ownership of the shared bus (20) and retry the bus transaction. Upon detecting the shared ARTRY* signal, all potential bus masters remove their bus requests and ignore any bus grants from the arbiter (14), thus allowing the snooping processor which asserted the ARTRY* signal to gain ownership of the shared bus (20) to perform the snoop copyback. The arbiter (14) provides simple arbitration support to guarantee the update of the memory (18) has the highest priority among masters ( 12, 16, 17).
Inventors
- 👤 James B. Gullette
- 👤 William C. Moyer
- 👤 Michael J. Garcia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:52
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
383 words
In a data processing system having a predetermined number of potential bus master devices, wherein each of said predetermined number of potential bus master devices accesses an external memory system via a plurality of shared buses, a method for implementing a bus arbitration protocol using an arbiter, coupled to each of said predetermined number of potential bus master devices, said arbiter receiving a plurality of bus request signals individually generated by said predetermined number of potential bus masters, and selectively asserting one of a plurality of bus grant signals in response thereto, to control allocation of bus ownership between each of said predetermined number of potential bus masters, said method comprising the steps of: asserting, via a first slave device, a first control signal and a second control signal in response to detecting an occurrence of a snoop hit during a first bus transaction initiated by a first master device on a first shared bus, said first control signal indicating that a data entry requested from said memory system by said first master device, during said first bus transaction, has been modified by said first slave device and that said memory system requires updating from said first slave device, said second control signal notifying said first master device to re-try said first bus transaction after said memory system has been updated by said first slave device; detecting, via said first master device and each of said predetermined number of potential bus master devices, assertion of said second control signal by said first slave device, said first master device terminating said first bus transaction by negating a first bus request signal, to allow said first slave device to assert a second bus request signal, and said first master device relinquishing ownership of said first shared bus by negating a third control signal in response to assertion of said second control signal, each of said predetermined number of potential bus master devices removing their individual bus request signals from said arbiter and ignoring any bus grant signal already received from said arbiter; and suppressing assertion of said bus request signals, by each of said predetermined number of potential bus master devices, until said first slave device receives a bus grant signal from said arbiter and initiates a second bus transaction to update said memory system.
Claim 2
Dependent Claim
383 words
In a data processing system having a predetermined number of potential bus master devices, wherein each of said predetermined number of potential bus master devices accesses an external memory system via a plurality of shared buses, a method for implementing a bus arbitration protocol using an arbiter, coupled to each of said predetermined number of potential bus master devices, said arbiter receiving a plurality of bus request signals individually generated by said predetermined number of potential bus masters, and selectively asserting one of a plurality of bus grant signals in response thereto, to control allocation of bus ownership between each of said predetermined number of potential bus masters, said method comprising the steps of: asserting, via a first slave device, a first control signal and a second control signal in response to detecting an occurrence of a snoop hit during a first bus transaction initiated by a first master device on a first shared bus, said first control signal indicating that a data entry requested from said memory system by said first master device, during said first bus transaction, has been modified by said first slave device and that said memory system requires updating from said first slave device, said second control signal notifying said first master device to re-try said first bus transaction after said memory system has been updated by said first slave device; detecting, via said first master device and each of said predetermined number of potential bus master devices, assertion of said second control signal by said first slave device, said first master device terminating said first bus transaction by negating a first bus request signal, to allow said first slave device to assert a second bus request signal, and said first master device relinquishing ownership of said first shared bus by negating a third control signal in response to assertion of said second control signal, each of said predetermined number of potential bus master devices removing their individual bus request signals from said arbiter and ignoring any bus grant signal already received from said arbiter; and suppressing assertion of said bus request signals, by each of said predetermined number of potential bus master devices, until said first slave device receives a bus grant signal from said arbiter and initiates a second bus transaction to update said memory system.
Claim 3
Dependent Claim
160 words
The method of claim 1 further comprising the steps of: asserting, via said arbiter, a first bus grant signal to grant ownership of said first shared bus to said first slave device, in response to said first master device negating said third control signal, said first slave device thereafter negating said first control signal and said second control signal and commencing said second bus transaction to update said memory system; re-asserting, via said first master device said first bus request signal to retry said first bus transaction and each of said predetermined number of potential bus master devices re-asserting their individual bus request signals, in response to said first slave device negating said first control signal and said second control signal; and granting, via said arbiter, said first master device ownership of said first shared bus, to allow said first master device to retry said first bus transaction, upon completion by said first slave device of said second bus transaction.
Claim 4
Dependent Claim
324 words
In a data processing system having a predetermined number of bus masters, wherein each of said predetermined number of potential bus masters accesses an external memory system via a plurality of shared buses, a method for implementing a snoop-retry bus arbitration protocol using an arbiter, coupled to each of said predetermined number of bus masters, to control allocation of bus ownership between each of said predetermined number of potential bus masters, said method comprising the steps of: asserting, via a snooping processor, a first control signal and a second control signal in response to detecting a snoop hit during a first bus transaction initiated by a first master device on a first shared bus, said first control signal indicating that a cache line requested from said memory system, during said first bus transaction, has been modified by said snooping processor and that said memory system requires updating by said snooping processor with a current version of said cache line, said second control signal notifying said first master device to relinquish ownership of said first shared bus and retry said bus transaction after said snooping processor updates said memory system; detecting, via said first master device and each of a predetermined number of potential bus masters, assertion of said second control signal, said first master device terminating said first bus transaction by negating a first bus request signal, and relinquishing ownership of said first shared bus by negating a third control signal in response to detecting assertion of said second control signal, said snooping processor asserting a second bus request signal to acquire bus ownership from said arbiter, each of said predetermined number of potential bus masters removing an individual bus request signal from said arbiter and ignoring any bus grant signal already received from said arbiter; and suppressing assertion, by each of said predetermined number of potential bus masters, of said bus request signal until said arbiter grants bus ownership to said snooping processor.
Claim 5
Dependent Claim
324 words
In a data processing system having a predetermined number of bus masters, wherein each of said predetermined number of potential bus masters accesses an external memory system via a plurality of shared buses, a method for implementing a snoop-retry bus arbitration protocol using an arbiter, coupled to each of said predetermined number of bus masters, to control allocation of bus ownership between each of said predetermined number of potential bus masters, said method comprising the steps of: asserting, via a snooping processor, a first control signal and a second control signal in response to detecting a snoop hit during a first bus transaction initiated by a first master device on a first shared bus, said first control signal indicating that a cache line requested from said memory system, during said first bus transaction, has been modified by said snooping processor and that said memory system requires updating by said snooping processor with a current version of said cache line, said second control signal notifying said first master device to relinquish ownership of said first shared bus and retry said bus transaction after said snooping processor updates said memory system; detecting, via said first master device and each of a predetermined number of potential bus masters, assertion of said second control signal, said first master device terminating said first bus transaction by negating a first bus request signal, and relinquishing ownership of said first shared bus by negating a third control signal in response to detecting assertion of said second control signal, said snooping processor asserting a second bus request signal to acquire bus ownership from said arbiter, each of said predetermined number of potential bus masters removing an individual bus request signal from said arbiter and ignoring any bus grant signal already received from said arbiter; and suppressing assertion, by each of said predetermined number of potential bus masters, of said bus request signal until said arbiter grants bus ownership to said snooping processor.
Claim 6
Dependent Claim
179 words
The method of claim 3 further comprising the steps of: asserting, via said arbiter, a first bus grant signal in response to said first master device negating said third control signal to relinquish ownership of said first shared bus, to grant ownership of said first shared bus to said snooping processor, said snooping processor thereafter negating said first control signal and said second control signal and commencing a second bus transaction to update said memory system; re-asserting, via said first master device said first bus request signal to retry said first bus transaction, and each of said predetermined number of potential bus master devices re-asserting their individual bus request signals, in response to said snooping processor negating said first control signal and said second control signal; detecting, via said arbiter, re-assertion of each individual bus request signal by said first master device and said predetermined number of potential bus master devices; and granting, via said arbiter, said first master device ownership of said first shared bus after said snooping processor updates said memory system during said second bus transaction.
Claim 7
Dependent Claim
70 words
The method of claim 3 wherein said step of detecting, via said first master device and each of a predetermined number of potential bus masters, assertion of said second control signal comprises the step of monitoring a shared signal line of a second shared bus, said shared signal line informing each of said predetermined number of potential bus masters notifying said first master device to terminate said first bus transaction.
Claim 8
Dependent Claim
50 words
The method of claim 3 wherein said step of suppressing assertion, by each of said predetermined number of potential bus masters, of said individual bus request signal occurs until said snooping processor detects said first shared bus is available and negates said first control signal and said second control signal.
Claim 9
Dependent Claim
319 words
In a data processing system having a predetermined number of bus masters each of which accesses an external memory system via a plurality of shared buses, a method for implementing a snoop-retry bus arbitration protocol using an arbiter, coupled to each of said predetermined number of bus masters, to control allocation of bus ownership between each of said plurality of shared buses, said method comprising the steps of: monitoring, via each of a number of potential bus masters, a first bus transaction performed by a first master device on a first shared bus to detect whether an address for a requested data entry is resident in a snooping one of said potential bus masters; providing, via said snooping one of said potential bus masters, a first control signal and a second control signal in response to said snooping one of said potential bus masters detecting that said address for said requested data entry is resident in said snooping one of said potential bus masters and that said requested data entry stored at said address has been modified; relinquishing, via said first master device, ownership of said first shared bus in response to receiving said second control signal by negating a third control signal, said first bus master thereafter removing a bus request signal from said arbiter; detecting assertion of said first control signal and said second control signal, via each of said potential bus masters, and removing said bus request signal generated by each of said potential bus masters from said arbiter, in response to detecting assertion of said second control signal, each of said potential bus masters thereafter ignoring any bus grant signal previously received from said arbiter; and suppressing assertion, by said first master device, of said bus request signal until said snooping one of said potential bus masters detects said first shared bus is available and negates said first control signal and said second control signal.
Claim 10
Dependent Claim
319 words
In a data processing system having a predetermined number of bus masters each of which accesses an external memory system via a plurality of shared buses, a method for implementing a snoop-retry bus arbitration protocol using an arbiter, coupled to each of said predetermined number of bus masters, to control allocation of bus ownership between each of said plurality of shared buses, said method comprising the steps of: monitoring, via each of a number of potential bus masters, a first bus transaction performed by a first master device on a first shared bus to detect whether an address for a requested data entry is resident in a snooping one of said potential bus masters; providing, via said snooping one of said potential bus masters, a first control signal and a second control signal in response to said snooping one of said potential bus masters detecting that said address for said requested data entry is resident in said snooping one of said potential bus masters and that said requested data entry stored at said address has been modified; relinquishing, via said first master device, ownership of said first shared bus in response to receiving said second control signal by negating a third control signal, said first bus master thereafter removing a bus request signal from said arbiter; detecting assertion of said first control signal and said second control signal, via each of said potential bus masters, and removing said bus request signal generated by each of said potential bus masters from said arbiter, in response to detecting assertion of said second control signal, each of said potential bus masters thereafter ignoring any bus grant signal previously received from said arbiter; and suppressing assertion, by said first master device, of said bus request signal until said snooping one of said potential bus masters detects said first shared bus is available and negates said first control signal and said second control signal.
Claim 11
Dependent Claim
161 words
The method of claim 7 further comprising the steps of: negating, via said snooping one of said potential bus masters, said first control signal and said second control signal, in response to detecting negation of said third control signal by said first master device, said snooping one of said potential bus masters thereafter commencing a second bus transaction to update said memory system with a modified data entry stored at said requested address; re-asserting, via said first bus master and each of said predetermined number of potential bus master devices, said individual bus request signal, in response to said snooping one of said potential bus masters negating said first control signal and said second control signal; detecting, via said arbiter, re-assertion of said bus request signal by said first master device; and granting, via said arbiter, said first master device ownership of said first shared bus upon completion by said snooping one of potential bus masters of a second bus transaction.
Claim 12
Dependent Claim
326 words
A data processing system, including a memory, for performing a snoop-retry bus arbitration protocol to control allocation of bus ownership for each of a predetermined number of shared buses, said data processing system comprising: first means for detecting assertion of each of a plurality of independent bus request signals and for selectively asserting in response thereto each of a plurality of independent bus grant signals; second means coupled to said first means and each of said predetermined number of shared buses, said second means being a first bus master of a first shared bus; third means coupled to said first means and each of said predetermined number of shared buses, said third means snooping a first bus transaction performed by said first bus master and asserting a first control signal and a second control signal, in response to detecting that a data entry requested by said second means during said first bus transaction has been modified and a copy of said modified data entry is resident in said third means, said second control signal notifying said first bus master to relinquish ownership of said first shared bus and to retry said bus transaction after said third means updates said memory system with said modified data entry, said second means negating a first bus request signal from said first means, in response to receiving said asserted second control signal from said third means; and fourth means coupled to said first means and each of a predetermined number of shared buses, said fourth means removing a second bus request signal from said first means in response to receiving said second control signal from said third means, said fourth means thereafter ignoring any bus grant signal already received from said first means, said second means and said fourth means suppressing re-assertion of their independent bus request signals until said third means detects said first shared bus is available and negates said first control signal and said second control signal.
Claim 13
Dependent Claim
326 words
A data processing system, including a memory, for performing a snoop-retry bus arbitration protocol to control allocation of bus ownership for each of a predetermined number of shared buses, said data processing system comprising: first means for detecting assertion of each of a plurality of independent bus request signals and for selectively asserting in response thereto each of a plurality of independent bus grant signals; second means coupled to said first means and each of said predetermined number of shared buses, said second means being a first bus master of a first shared bus; third means coupled to said first means and each of said predetermined number of shared buses, said third means snooping a first bus transaction performed by said first bus master and asserting a first control signal and a second control signal, in response to detecting that a data entry requested by said second means during said first bus transaction has been modified and a copy of said modified data entry is resident in said third means, said second control signal notifying said first bus master to relinquish ownership of said first shared bus and to retry said bus transaction after said third means updates said memory system with said modified data entry, said second means negating a first bus request signal from said first means, in response to receiving said asserted second control signal from said third means; and fourth means coupled to said first means and each of a predetermined number of shared buses, said fourth means removing a second bus request signal from said first means in response to receiving said second control signal from said third means, said fourth means thereafter ignoring any bus grant signal already received from said first means, said second means and said fourth means suppressing re-assertion of their independent bus request signals until said third means detects said first shared bus is available and negates said first control signal and said second control signal.
Claim 14
Dependent Claim
31 words
The data processing system of claim 9 further comprising a memory system coupled to said second means, said third means, and said fourth means, via said predetermined number of shared buses.
Claim 15
Dependent Claim
79 words
The data processing system of claim 9 wherein said first means comprises an arbiter for supporting a snoop copyback update of said memory system by said third means, said arbiter asserting a second bus grant signal to grant ownership of said first shared bus to said third means, in response to said third means detecting that said data entry has been modified and requesting bus mastership from said arbiter and said second means negating said first bus request signal.
Claim 16
Dependent Claim
56 words
The data processing system of claim 9 wherein said second means and said fourth means suppress assertion of their independent bus request signals, until said third means negates said first control signal and said second control signal, to enable said first means to grant bus mastership to said second means to retry said first bus transaction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-09 | 1999-10-09 | 2000-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-09 | 2003-10-09 | 2004-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-09 | 2007-10-09 | 2008-04-09 | $7700.00 | Window Closed / Lapsed |