EP0425843A2
Expired / Lapsed
EP
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Enhanced locked bus cycle control in a cache memory computer system
Assignee: Compaq Computer Corp
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Filing: 1990-10-08
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Granted: —
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Expires: 2010-10-08
Abstract
Abstract An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the controller 12 but control of the system bus 14 by controller 12 is maintained by inhibiting hold requests to the controller 12 by other system elements.
Inventors
- 👤 Paul R. Culley
- 👤 Mark E. Taylor
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 01:57
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
147 words
A processor lock cycle control system adapted for use with a computer system of the type including a processor which executes certain instructions in locked bus cycles by issuing a bus lock signal to a cache control circuit, a cache memory system including a cache memory control circuit, and a system bus wherein the cache control circuit interfaces between the processor and the system bus to control access to the bus by the processor, and wherein the system includes one or more system elements sharing the system bus with the processor, control of the bus ordinarily being transferred from the control circuit to other system elements in response to a bus request signal, said lock cycle control system comprising: means for selectivity disabling processor bus lock signals; means for inhibiting bus request signals from other system elements to the cache control circuit during processor locked bus cycles.
Claim 2
Dependent Claim
147 words
A processor lock cycle control system adapted for use with a computer system of the type including a processor which executes certain instructions in locked bus cycles by issuing a bus lock signal to a cache control circuit, a cache memory system including a cache memory control circuit, and a system bus wherein the cache control circuit interfaces between the processor and the system bus to control access to the bus by the processor, and wherein the system includes one or more system elements sharing the system bus with the processor, control of the bus ordinarily being transferred from the control circuit to other system elements in response to a bus request signal, said lock cycle control system comprising: means for selectivity disabling processor bus lock signals; means for inhibiting bus request signals from other system elements to the cache control circuit during processor locked bus cycles.
Claim 3
Dependent Claim
78 words
The system of claim 1, further comprising means for causing the system to operate in one of three modes of processor lock cycle operation, wherein: a. in mode one all processor lock cycle signals are passed to said cache controller; b. in mode two all processor lock cycle signals are inhibited; c. in mode three processor lock cycles are selectively disabled and bus request signals to said controller are inhibited during execution of lock cycles by the processor.
Claim 4
Dependent Claim
51 words
The system of claim 2, wherein said mode selection means comprises: a mode selection register including at least two status bits, the value of said status bits being subject to control by the processor; and means for generating mode selection output signals based upon the status of said mode selection register.
Claim 5
Dependent Claim
29 words
The system of claim 3, wherein said mode selection signal means includes means for generating a two-bit output coded signal to select the mode of processor lock cycle operation.
Claim 6
Dependent Claim
267 words
The system of claim 4, wherein: said mode selection signal means provides a binary LOCKMOD signal and binary LOCKINH signal which in combination indicate the selected mode of operation; said processor provides an output PRDY signal to indicate completion of a bus cycle; said processor provides a PLOCK* output signal to indicate an active processor locked bus cycle; said system includes means for generating a HOLD D signal in response to active bus request signals to said controller from other system elements; means for providing inverted LOCKMOD, LOCKINH, PLOCK* input signals, said inverted signals being designated LOCKMOD*, LOCKINH* and PLOCK, respectively; wherein said means for selectively disabling processor lock signals and said means for inhibiting bus request signals comprises a logic circuit means for generating a LOCKEN* output signal to selectively disable processor bus cycle lock signals to said controller, and a HOLD D output signal to selectively inhibit hold requests to said controller, said logic circuit receiving as inputs the LOCKMOD, LOCKMOD*, PLOCK, PLOCK*, PRDY, PRDY*, HOLD D and a system clock synchronizing ZCLK signal and providing output control signals LOCKEN and HOLD 0̸ in accordance with the following logic sequence: HOLD O = HOLD D* /MLOCK + HOLD D * HOLD O; LOCKEN = HOLD D * /MLOCK * /BLOCK + LOCKEN * HOLD D * /BLOCK + LOCKEN * PLOCK * /PRDY * /BLOC + ENABLE; Where: MLOCK = LOCKMOD * PLOCK, BLOCK + /LOCKMOD * LOCKINH, ENABLE = /LOCKMOD * LOCKINH; where, in the foregoing logic equation, "*" indicates the AND function, "+" indicates the OR function, and "/" indicates the INVERSE function.
Claim 7
Independent Claim
151 words
A method of controlling the processor locked bus cycle operation of a computer system including a processor of the type which issue bus lock cycle signals to prevent loss of control of the bus during certain instruction sequences, a cache memory, a cache memory controller and a system bus wherein the controller interfaces between the processor and the system bus to control access to the bus by the processor and wherein the system includes one or more system elements sharing control of the bus with the processor and cache controller control of the bus being transferred from the controller to such other system elements in response to a bus request signal, said locked bus cycle control method comprising the steps of: selectively disabling processor bus locked cycle signals; inhibiting bus request signals from other system elements to the cache controller while the processor is executing instructions in a bus locked mode.
Claim 8
Independent Claim
151 words
A method of controlling the processor locked bus cycle operation of a computer system including a processor of the type which issue bus lock cycle signals to prevent loss of control of the bus during certain instruction sequences, a cache memory, a cache memory controller and a system bus wherein the controller interfaces between the processor and the system bus to control access to the bus by the processor and wherein the system includes one or more system elements sharing control of the bus with the processor and cache controller control of the bus being transferred from the controller to such other system elements in response to a bus request signal, said locked bus cycle control method comprising the steps of: selectively disabling processor bus locked cycle signals; inhibiting bus request signals from other system elements to the cache controller while the processor is executing instructions in a bus locked mode.
Claim 9
Independent Claim
382 words
A method of controlling the processor locked bus cycle operation of a computer system including a processor of the type which issue bus lock cycle signals to prevent loss of control of the bus during certain instruction sequences, a cache memory, a cache memory controller and a system bus wherein the controller interfaces between the processor and the system bus to control access to the bus by the processor and wherein the system includes one or more system elements sharing control of the bus with the processor and cache controller control of the bus being transferred from the controller to such other system elements in response to a bus request signal, said locked bus cycle control method comprising the steps of: a. setting a locked cycle mode of operation to one of three modes; b. in mode one, passing all processor bus lock signals to the cache controller; c. in mode two, blocking all processor bus lock signals. d. in mode three, processing processor bus lock signals in accordance with the following logic scheme: i. when the cache controller has control of the bus and an active processor bus lock signal is asserted, blocking the bus lock signal to the cache controller and inhibiting bus request signals from other system elements until the processor complete the locked bus cycle; ii. when the cache controller has control of the bus but a bus request signal is pending when an active processor bus lock signal is asserted, passing the bus lock signal to the cache controller and continuing the bus request signal; when the bus request signal is negated, blocking the bus lock signal to the cache controller and inhibiting bus request signals to the cache controller; iii. when the cache controller does not have control of the bus when an active processor bus lock signal is asserted passing the bus lock signal to the controller, and continuing the bus request signal; thereafter when the bus request signal is negated, blocking the bus lock signal to the cache controller and inhibiting bus request signals to the cache controller; iv. when a bus request signal to the cache controller and an active processor bus lock cycle signal are asserted simultaneously, passing the bus lock signal to the cache controller and continuing the bus request signal.
Claim 10
Independent Claim
382 words
A method of controlling the processor locked bus cycle operation of a computer system including a processor of the type which issue bus lock cycle signals to prevent loss of control of the bus during certain instruction sequences, a cache memory, a cache memory controller and a system bus wherein the controller interfaces between the processor and the system bus to control access to the bus by the processor and wherein the system includes one or more system elements sharing control of the bus with the processor and cache controller control of the bus being transferred from the controller to such other system elements in response to a bus request signal, said locked bus cycle control method comprising the steps of: a. setting a locked cycle mode of operation to one of three modes; b. in mode one, passing all processor bus lock signals to the cache controller; c. in mode two, blocking all processor bus lock signals. d. in mode three, processing processor bus lock signals in accordance with the following logic scheme: i. when the cache controller has control of the bus and an active processor bus lock signal is asserted, blocking the bus lock signal to the cache controller and inhibiting bus request signals from other system elements until the processor complete the locked bus cycle; ii. when the cache controller has control of the bus but a bus request signal is pending when an active processor bus lock signal is asserted, passing the bus lock signal to the cache controller and continuing the bus request signal; when the bus request signal is negated, blocking the bus lock signal to the cache controller and inhibiting bus request signals to the cache controller; iii. when the cache controller does not have control of the bus when an active processor bus lock signal is asserted passing the bus lock signal to the controller, and continuing the bus request signal; thereafter when the bus request signal is negated, blocking the bus lock signal to the cache controller and inhibiting bus request signals to the cache controller; iv. when a bus request signal to the cache controller and an active processor bus lock cycle signal are asserted simultaneously, passing the bus lock signal to the cache controller and continuing the bus request signal.
Claim 11
Independent Claim
111 words
A method of controlling the processor locked bus cycle operation of a computer system including a processor of the type which issue bus lock cycle signals to prevent loss of control of the bus during certain instruction sequences, a cache memory, a cache memory controller and a system bus wherein the controller interfaces between the processor and the system bus to control access to the bus by the processor and wherein the system includes one or more system elements sharing control of the bus with the processor and cache controller control of the bus being transferred from the controller to such other system elements in response to a bus request signal.
Claim 12
Independent Claim
111 words
A method of controlling the processor locked bus cycle operation of a computer system including a processor of the type which issue bus lock cycle signals to prevent loss of control of the bus during certain instruction sequences, a cache memory, a cache memory controller and a system bus wherein the controller interfaces between the processor and the system bus to control access to the bus by the processor and wherein the system includes one or more system elements sharing control of the bus with the processor and cache controller control of the bus being transferred from the controller to such other system elements in response to a bus request signal.
References Cited (Backward Citations)
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